vcc vss esd protection circuit

[surreyian]

esd protection circuit

when doing esd design for vdd/vss, we use the gate grounded NMOS. why is it so?
i also came across design that have a R at its gate and tie to GND. what is the difference? what is the advantage of using the R? is it to provide a low impedance path? or is it to prevent ruptures of the oxide.
thanks

 

[malizevzek]

2kv protection circuit

in esd design one uses diode connected NMOS for connection with Vss, and diode connected PMOS for connection with Vdd, so the gates of these transistors are connected to Vss and Vdd, respectively.

 

[Abaoapple]

esd parastic cap

it is said the GRNMOS have a low broken voltage than GGNMOS

so it can prerect the IC early

but i still dont know the result

 

[rajkumaru]

diode protection vcc

Qus- when doing esd design for vdd/vss, we use the gate grounded NMOS. why is it so?
Ans- To protect the circuit from ESD event by using either up-and-down diode or GGNMOS.
Qus- i also came across design that have a R at its gate and tie to GND. what is the difference? what is the advantage of using the R? is it to provide a low impedance path?
Ans- resitor provide high resistance path so high current (ESD is current phenomenon) will not pass through the PMOS/NMOS device and it can be protected. As you know, for excess current already we design a path of low resistance.

 

[llbaobao]

esd protection circuitry

Qus- when doing esd design for vdd/vss, we use the gate grounded NMOS. why is it so?
Ans- To protect the circuit from ESD event by using either up-and-down diode or GGNMOS.
Qus- i also came across design that have a R at its gate and tie to GND. what is the difference? what is the advantage of using the R? is it to provide a low impedance path?
Ans- resitor provide high resistance path so high current (ESD is current phenomenon) will not pass through the PMOS/NMOS device and it can be protected. As you know, for excess current already we design a path of low resistance.

>what is the advantage of using the R?
Besides provide high resistance path so high current (ESD is current phenomenon) will not pass through the PMOS/NMOS device and it can be protected, the value and shape of the R is important. Escepially to the ESD unit of VSS/VDD. the R and its parasitic cap delayed the pulse, and increase the ESD capability.

 

[ESDSolutions]

protection circuit vcc

Grounded Gate NMOS (ggNMOS) is used for ESD protection in mature processes. The idea is that the device must have low leakage during normal operation, hence the gate is tied low. When -during ESD- the drain voltage is increased above the standard signal conditions, the drain-substrate junction goes into avalanche breakdown which ultimately leads to the turn-on of the parasitic NPN device between Drain (collector) - Substrate (base) - Source (emitter). This device has ~10 times more current capability as compared to the active MOS device and can shunt the excess charges to ground.

When a resistance (kilo ohm) is tied between gate and source, the gate potential is capacitively (Drain-gate cap) coupled high during the fast ESD pulse. This induces a small amount of MOS current through the channel which will lead to faster turn-on of the parasitic NPN. This means that the voltage between pad and ground will be smaller when a gate resistance is used.

Take Care: For ESD protection for 90nm and more advanced the ggNMOS solution is not preferred anymore due to the high trigger voltage and holding voltage compared to the breakdown voltage of a thin gate oxide device. A paper from IBM showed that from 90nm on it is possible that the ggNMOS cannot even protect its own gate oxide anymore during ESD stress. New proprietary solutions (not free to use without some license) are used to cope with ESD in advanced technologies

Also in high voltage technologies, ggNMOS devices are not being used for ESD protection due to degradation effects under ESD pulses.

 

[tdy]

esd protection circuits

a res reduce peak transient drain voltage by turning on the channel with help from parasitic cgs cap.

 

[Anbusivam]

esd circuit for vcc

Dear ESDSolutions. Very well explained. Thanks for helping me understand ggnmos better.

 

[mengcy]

diodes vdd vss

Hi,ESDSolutions,what do you mean by "degradation effects under ESD pulses. "?

 

[ESDSolutions]

esd protection circuit design

Hi Mengcy

What I mean with "degradation effects" is that the ggNMOS device is degrading under multiple ESD stress pulses. This is typical for High Voltage CMOS nodes.

For instance: Suppose the foundry provides a specific ESD layout of a high voltage NMOS device. The foundry will claim a 4kV HBM robustness level of the specific layout (L, W, ..) (just an example).

When this device is stressed with 2kV HBM you expect perfect protection even for multiple sequential stress pulses. However, what you will see is that the leakage between drain and substrate will slowly increase.

Suppose the leakage at the drain is about 1nA (@32V bias) before the stress test starts. Then the device is stressed with 2kV HBM pulses while the leakage current is monitored in between the HBM pulses. You will see that the leakage is increasing slowly from nA to uA to mA. At some time it will degrade to a short circuit. This can happen already at 10-50 pulses.

When the foundry or IO partner or ESD IP/consultant gives you a HV NMOS layout you should ALWAYS ask for "repetitive stress test" results!

A recent paper shows an example of such data:
"High-Voltage nLDMOS in Waffle Layout Style with Body- Injected Technique for ESD Protection" by Wen-Yi Chen and Ming-Dou Ker published in IEEE Electron Device Letters - EDL.

ES