snr_vlsi
Member level 1
Hi
Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?
How do you optimize skew/insertion delays in CTS?
What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree Synthesis)?
What constraints you add in CTS (Clock Tree Synthesis) for clock gates?
What do clock constraints file contain?
How to analyze clock tree reports?
How do you minimize clock skew/ balance clock tree
thx
snr_vlsi
Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?
How do you optimize skew/insertion delays in CTS?
What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree Synthesis)?
What constraints you add in CTS (Clock Tree Synthesis) for clock gates?
What do clock constraints file contain?
How to analyze clock tree reports?
How do you minimize clock skew/ balance clock tree
thx
snr_vlsi