Variable number of inputs in a Verilog module

[vikasvij1982]

Hi,

I wanted to code a generalized module for a project in which based on the parameters the number of inputs can vary. I know how to have different bit widths based on parameters, but not number of inputs.

As an example, if i want to have a module M1 which can have only in1 as input or it can also have in2, or in3 as inputs and this input selection is done by parameter.

---

Code Verilog - [expand]
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module #(parameter in2_select = 0, parameter in3_select = 0) M1
(
if(in2_select)
input in2,
 
if(in3_select)
input in3,
 
input in1,
 
output out
);

---

Can i do something like that?? Or is there any way i can do overloading of the module name in Verilog??

Thanks for any help you can provide

Vikas

 

[permute]

I'm not sure if verilog supports things like: "input [N-1:0] x [1:W]" if not, you might just do this by having an input [N*W-1:0].

 

[vikasvij1982]

Thanks permute for the quick reply, but what i meant with the question was that if i have a new pin name instead of a bus kind of representation for the inputs. That is why i was stating in1, in2 and in3.

If i am not clear then please let me know

Vikas

 

[ljwfred]

actually i have never seen that before.
but i have seen something using define instead.

    output wire                       cclk_0,      // controller clock output
    input  wire                       ctl_rst_n,
    input  wire [2              -1:0] msd_tie,     // tie-hi:tie-low i.e. 2'b10
`ifdef DWC_DDR3PHY_ITMC_D2
    input  wire                       mode_sel,    // mode select
`endif