woeichee
Newbie level 5
i have a design that require to run on variable frequency of clk(sampling rate), in the range of 8kHz to 216kHz.
My question are:
1. How to write the sdc?
2. Other than sdc, is there any thing(circuit, etc) need to be take care or add in?
thanks
My question are:
1. How to write the sdc?
2. Other than sdc, is there any thing(circuit, etc) need to be take care or add in?
thanks