buenos
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Hi
On the Xilinx Spartan-6 FPGA docs, they say we can clock the MGTs from:
-fullchip global clock,
-BUFPLL routing, which supposed to be low-jitter.
-Dedicated MGT clock pin
-dedicated routing from neighbor MGT
For the first one, they say its noise, and i can imagine that. The first two, they say are available for factory test purposes only. why is that? The last option is not really available for me, and the third option would require me to have an external clock chip on board, which is what i want to avoid.
It would look stupid to route an on-chip already available clock to an io pin, then route it on-board to the GTP clock input. I cant see how it woul have less jitter than a global clock.
so, what would be the way to source the GTP clock pin from an already available clock in the FPGA?
should i design with using BUFPLL? even when the xilinx datasheet says not to use it?
or, do i have to put the clock chip on board anyway? like this one: Ultra Low Jitter Synthesizer and Jitter Cleaner - Internal VCO Output - CDCM61001 - TI.com
These Spartan 6 FPGAs have lots of special clock routings and PLLs built-in, it would be a shame if i couldnt make use of them for the GTP reference clock.
On the Xilinx Spartan-6 FPGA docs, they say we can clock the MGTs from:
-fullchip global clock,
-BUFPLL routing, which supposed to be low-jitter.
-Dedicated MGT clock pin
-dedicated routing from neighbor MGT
For the first one, they say its noise, and i can imagine that. The first two, they say are available for factory test purposes only. why is that? The last option is not really available for me, and the third option would require me to have an external clock chip on board, which is what i want to avoid.
It would look stupid to route an on-chip already available clock to an io pin, then route it on-board to the GTP clock input. I cant see how it woul have less jitter than a global clock.
so, what would be the way to source the GTP clock pin from an already available clock in the FPGA?
should i design with using BUFPLL? even when the xilinx datasheet says not to use it?
or, do i have to put the clock chip on board anyway? like this one: Ultra Low Jitter Synthesizer and Jitter Cleaner - Internal VCO Output - CDCM61001 - TI.com
These Spartan 6 FPGAs have lots of special clock routings and PLLs built-in, it would be a shame if i couldnt make use of them for the GTP reference clock.
