Using Ethernet for point to point link between two FPGAs

[dspfpgadevelop]

Hi,

I need to transfer data between two Xilinx FPGAs.
The only connection available is via an Ethernet cable. The FPGAs are connected each to a PHY.

I have designed a simple block that uses an EMAC inside the FPGA to send and receive Ethernet packets.

I am not using any protocol other that Ethernet. No IP, UDP or TCP, just raw Ethernet frames.

Data transfer works most of the time but I seem to be getting a few bit errors now and again and can't identify where they come from. I have tried various cables and cooling down the FPGAs and PHY, no result. Also I checked the FPGA<->PHY interface carefully and I am pretty sure there is no problem there.

My question is this:

Is it possible to transmit data with 0% error at all when going: EMAC->PHY -> Ethernet cable -> PHY->EMAC? Or should I expect to always have some errors!?

Thanks

 

[Maxwell077]

You can be sure about it. My friend does the same job and he hasn't got any errors.. And, his frames are also UDP packed..
he used Virtex 5 ML506 FPGA and PHY..

 

[noman4ever]

can u please provide the working code of ethernet on virtex 5. I am doing the communication b/w pc and fpga using ethenet mac lite core, it works but when i sent more than one packet from pc like 2 packets, i only get one packet on fpga. plz help

 

[lucbra]

If you want to be 100% sure about getting no errors, you will need to implement some sort of CRC. UDP as such is not enough, but can be used a carrier protocol to implement your data check.

An other way is to implement a full TCP/IP stack. this ensures error free data transmission.

Regards,
L

 

[FvM]

No data transmission can be error-free, strictly spoken. You get different likelihood of undetected respectively uncorrected errors
depending on the amount of redundance introduced by the data integrity layer (e.g. CRC) and the channel's error rate. Analyzing
ethernet transmission, the first data integrity check is already implemented on the PHY layer by 4b/5b encoding of data. MAC CRC, usually
enabled in the MAC hardware is the next, followed by IP checksum and UDP or TCP integrity checks. Finally, the application layer may
add CRC on it's own.

Referring to the original question, observing bit errors at the PHY layer without frequent receive errors reported by the PHY receiver
suggests rather timing errors in the PHY interface (incorrect designed logic) than transmission errors at the ethernet medium. On the other
hand, if you ignore existing receiver errors (cause by electrical interferences or bad media), you must be aware of occasional undetected
bit errors.