Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

USELOWSKEWLINES Constraint!

Status
Not open for further replies.

kala

Newbie level 4
Joined
Jun 29, 2005
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,324
net uselowskewlines

Hi,

As i don't have enough BUFG, i'm using simple IBUF to my clock signal. Can i use USELOWSKEWLINES constrint along with MAXSKEW constraint for the same clock signal?

eg.
NET "p1_sck_sig" USELOWSKEWLINES;
NET "p1_sck_sig" MAXSKEW = 1 ns;

Regards,
kaka
 

uselowskewlines

yes, it works.

zcq
 

Yeah I have done it and it worked, yet it depends on the fanout mainly, if you have a clock feeding 100 logic cell I doubt that you can get less than 1 ns skew,
yet you may give it a try.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top