nishanthpv
Junior Member level 2
Hai,
I want to make the layout of a delay element. So first i made the layout of an inverter. And i used the symbol in the schematic of delay element and from that i generated the layout. Next i want to do some optimization using hierarchy. For example i wanted to make the nwell common for all pmos transistors and use long bar of substrate contacts. But what i found is that the base file also get edited (Inverter layout is replaced by delay element layout). So anybody can suggest a solution for this problem?...
Thanks in advance
Nishanth P.V
I want to make the layout of a delay element. So first i made the layout of an inverter. And i used the symbol in the schematic of delay element and from that i generated the layout. Next i want to do some optimization using hierarchy. For example i wanted to make the nwell common for all pmos transistors and use long bar of substrate contacts. But what i found is that the base file also get edited (Inverter layout is replaced by delay element layout). So anybody can suggest a solution for this problem?...
Thanks in advance
Nishanth P.V