urgent(sdf back annotation)

[snr_vlsi]

Hi,

This is in reference to annotating delays through sdf on a hierarchial design.

I have an hierarchial design with three subdesigns. I want to annotate the delay of these three subdesigns to the top design.

I have written out sdf files for each subdesign through design compiler.

Now, when I want to read all the three subdesign sdf files together, each time I have to change the current design to the respective subdesign and then read in the corresponding subdesign. Is there anyway where in I can read in all the three subdesign sdf files together without using current_design command in design compiler.

Now after reading in all the three subdesign sdf file, when I write the sdf file for the top design, there is a problem.

The delays present in each subdesign sdf file and the top design sdf file are not matching.

How to solve this.

Thx
snr_vlsi

 

[ivlsi]

Has the problem been resolved?

 

[tariq786]

dude do

write_sdf filen_name # this will write sdf for the whole design

write_sdf -instance_name "give instance name" filename2 #this will write sdf for the sub-design.


For details, please look for write_sdf help under design compiler

 

[ivlsi]

Is there a special reason to write SDF for just sub-instances and not for the whole design?

 

[tariq786]

Is there a special reason to write SDF for just sub-instances and not for the whole design?

Yes. In this case, you want to check timing of a block that you are interested in, not the whole design. This could be much faster than timing of the whole design.

 

[ivlsi]

Are you talking about the time needed to back-annotate the design? As soon as the design is back-annotated, the timing checks should take the same time... Am I wrong?

 

[tariq786]

Are you talking about the time needed to back-annotate the design? As soon as the design is back-annotated, the timing checks should take the same time... Am I wrong?

you are right. Please do more research then ask further questions.