EEPuppyPuppy
Junior Member level 3
Hi, I am designing a build-in calculation ternary memory cell, which has a structure containing two 6T-SRAM-like circuits as well as some other parts for calculation purposes. And I have a bit-line voltage drop problem which I do not want and also do not know why the drop happens.
Like SRAM, the memory cell I am working on also has bit-lines. The circuit of the unit memory cell has two bit-lines and will be precharged to Vdd before starting to read.
A problem I am facing right now is that there will be a certain amount of voltage drop at the moment when the reading starts. And the unit cells need to be put together so the voltage drop will accumulate. Hope anyone could give me some suggestions about the possible problem that leads to the sudden unwanted voltage drop.
The image attached here might help explain the situation I am facing.
More details about how I made the design and simulation:
- I did several HSpice simulations on the netlist (CMOS) and everything works fine with either a single cell or a cell column which has 32 single cells sharing the same bit-lines.
The simulation I did is the transient simulation. To simulate the reading phase, I set the initial voltage of both bit-lines to Vdd to simulate the recharging. I also set the initial voltages of the internal storage node inside the cell circuit to simulate the data stored in the cell. (Take SRAM as an example, I set the bit-line to Vdd and those two storage nodes to 0 and 1.)
- Later, I use Cadence Virtuoso to draw the schematic and the layout for a single cell. I also did RC extraction on the single cell and get HSpice files based on the RC extraction and redo the simulation. From there I noticed that right at the beginning of the reading, there is a very small voltage drop. The drop is so small so I felt it should be fine.
For the HSpice files I got from RC extraction, there are three files '.pex', '.pxi', and '.netlist'. I noticed that except for the external pins I specified in the circuit such as bit-lines and word-line still keep their names in the new netlist, the internal nodes all get divided into many subnodes. For example, one of the storage nodes NET014 becomes N_NET014_c_201_p, N_NET014_MM0_g, ... So when I do the simulation on the RC extracted netlist, I set the initial voltage for some of the subnodes of NET014. I only set some of them is because I found that the circuit does not work at all when some certain subnodes got the initial voltage set. (The subnode N_NET014_c_201_p should not get the initial voltage set but N_NET014_MM0_g should get the initial voltage set)
- Then, I made a cell column which contains 32 unit cells in Cadence Virtuoso with RC extraction. In the HSpice simulation result, I can see a very phenomenal sharp voltage drop at the beginning of the reading. The precharge is to 1 V. What I expected to see is that both bit-lines are around 1 V at time=0 ns and start to drop the voltage gradually or maintain its voltage based on the value stored in the cells and what I want to read. However, what I see is the bit-line voltages drop to some value lower than 0.5 V at time=0 ns. So when I did the simulation on the single cell, the drop is so small. But when put 32 cells into a column, the beginning voltage drop is a nightmare.
Since the way to know the exact value from the cell is based on the voltage drop scale, the beginning voltage sudden voltage drop really gives me troubles. For example, say that focus one bit-line during the reading phase, if the voltage drop is ΔV from Vdd, the output, (Vdd - ΔV), stands for a reading value 1. Vdd is the voltage that the bit-line got precharged to. My Vdd is designed to be 1 V. If the voltage drop is 2*ΔV, the output one the bit-line is (Vdd - 2*ΔV) which has the meaning of 2. In this case, I might design the circuit so that ΔV = 0.7 V. Now my circuit does not start from Vdd = 1 V but it starts from 0.45 V, the designed ΔV becomes smaller, such as 0.3 V, which is very not practical. Also, since the voltage drop is not exactly linear for value 1 to 10 (Voltage drop from 9 to 10 is kind of smaller than the voltage drop from 0 to 1), not starting from Vdd make it even harder to design the value for ΔV.
I also face some incorrect voltage drops during reading which I suspect might also because of the unwanted sudden voltage drop at the beginning.
Really sorry for the long story. Really hope someone could give me any suggestions.
Thank you
Like SRAM, the memory cell I am working on also has bit-lines. The circuit of the unit memory cell has two bit-lines and will be precharged to Vdd before starting to read.
A problem I am facing right now is that there will be a certain amount of voltage drop at the moment when the reading starts. And the unit cells need to be put together so the voltage drop will accumulate. Hope anyone could give me some suggestions about the possible problem that leads to the sudden unwanted voltage drop.
The image attached here might help explain the situation I am facing.
More details about how I made the design and simulation:
- I did several HSpice simulations on the netlist (CMOS) and everything works fine with either a single cell or a cell column which has 32 single cells sharing the same bit-lines.
The simulation I did is the transient simulation. To simulate the reading phase, I set the initial voltage of both bit-lines to Vdd to simulate the recharging. I also set the initial voltages of the internal storage node inside the cell circuit to simulate the data stored in the cell. (Take SRAM as an example, I set the bit-line to Vdd and those two storage nodes to 0 and 1.)
- Later, I use Cadence Virtuoso to draw the schematic and the layout for a single cell. I also did RC extraction on the single cell and get HSpice files based on the RC extraction and redo the simulation. From there I noticed that right at the beginning of the reading, there is a very small voltage drop. The drop is so small so I felt it should be fine.
For the HSpice files I got from RC extraction, there are three files '.pex', '.pxi', and '.netlist'. I noticed that except for the external pins I specified in the circuit such as bit-lines and word-line still keep their names in the new netlist, the internal nodes all get divided into many subnodes. For example, one of the storage nodes NET014 becomes N_NET014_c_201_p, N_NET014_MM0_g, ... So when I do the simulation on the RC extracted netlist, I set the initial voltage for some of the subnodes of NET014. I only set some of them is because I found that the circuit does not work at all when some certain subnodes got the initial voltage set. (The subnode N_NET014_c_201_p should not get the initial voltage set but N_NET014_MM0_g should get the initial voltage set)
- Then, I made a cell column which contains 32 unit cells in Cadence Virtuoso with RC extraction. In the HSpice simulation result, I can see a very phenomenal sharp voltage drop at the beginning of the reading. The precharge is to 1 V. What I expected to see is that both bit-lines are around 1 V at time=0 ns and start to drop the voltage gradually or maintain its voltage based on the value stored in the cells and what I want to read. However, what I see is the bit-line voltages drop to some value lower than 0.5 V at time=0 ns. So when I did the simulation on the single cell, the drop is so small. But when put 32 cells into a column, the beginning voltage drop is a nightmare.
Since the way to know the exact value from the cell is based on the voltage drop scale, the beginning voltage sudden voltage drop really gives me troubles. For example, say that focus one bit-line during the reading phase, if the voltage drop is ΔV from Vdd, the output, (Vdd - ΔV), stands for a reading value 1. Vdd is the voltage that the bit-line got precharged to. My Vdd is designed to be 1 V. If the voltage drop is 2*ΔV, the output one the bit-line is (Vdd - 2*ΔV) which has the meaning of 2. In this case, I might design the circuit so that ΔV = 0.7 V. Now my circuit does not start from Vdd = 1 V but it starts from 0.45 V, the designed ΔV becomes smaller, such as 0.3 V, which is very not practical. Also, since the voltage drop is not exactly linear for value 1 to 10 (Voltage drop from 9 to 10 is kind of smaller than the voltage drop from 0 to 1), not starting from Vdd make it even harder to design the value for ΔV.
I also face some incorrect voltage drops during reading which I suspect might also because of the unwanted sudden voltage drop at the beginning.
Really sorry for the long story. Really hope someone could give me any suggestions.
Thank you
