Unresolved hierarchical reference

[sonaj]

I would like to see the inside of a module, without using a port

module submodule (a,b,c);
 .
 .
 reg subtest;
 .
 .
 .
endmodule

module _main (testout);

 submodule _sm(a,b,c);

 assign testout=_main._sm.subtest;

endmodule

synplify report error: Unresolved hierarchical reference _main._sm.subtest

I do not want ports to be used only for testing board (not simulation).

 

[permute]

I suspect there is some other token than "_main" that needs to be used. that said, I think the idea itself is bad.