ChrisRR
Newbie level 6
FSMD Design
I have been learning how to write VHDL using the book "FPGA prototyping by VHDL examples: Xilinx Spartan-3 version" and I'm working through the FSMD design examples and loading testbench vectors from external files and writing the output data to text files to quickly view without having to check the waveforms.
But in my output I was getting some unexpected values in the fibonnaci example. Here's the waveform. **broken link removed**
So when I put the value 08 into the component I expected to get the output 15 (hex) but instead get FFFFF. I see from the waveform that when I sample right on the rising edge of done_tick the data output is changing from 15 to FFFFF. Is this FFFFF output just a product of the simulator and it would run correctly in synthesis or would the clock propogation cause the value to still be FFFFF in synthesis?
If you need to see the code I can post it here but the book is also available on Google Books, starting page 140
Thanks
I have been learning how to write VHDL using the book "FPGA prototyping by VHDL examples: Xilinx Spartan-3 version" and I'm working through the FSMD design examples and loading testbench vectors from external files and writing the output data to text files to quickly view without having to check the waveforms.
But in my output I was getting some unexpected values in the fibonnaci example. Here's the waveform. **broken link removed**
So when I put the value 08 into the component I expected to get the output 15 (hex) but instead get FFFFF. I see from the waveform that when I sample right on the rising edge of done_tick the data output is changing from 15 to FFFFF. Is this FFFFF output just a product of the simulator and it would run correctly in synthesis or would the clock propogation cause the value to still be FFFFF in synthesis?
If you need to see the code I can post it here but the book is also available on Google Books, starting page 140
Thanks