Understanding ESD rating of device

[FreshmanNewbie]

I have this device

My system experienced an ESD event up stream of the 3.3V supply line.

The chip locks up after this event.

The scoping of the power supply lines measured a spike of > 200 volts caused by this event.

The chip is rated for ESD protection >8kV, but unsure if I understand this rating correctly.

 

[KlausST]

Hi,

3.3V ppower supply lines should be bypassed with capacitors. They usually are big enough to suppress an ESD pulse.
I don't get how there can be 200V at the power supply lines.
I suspect a measurement problem.

Still wrong capacitor placement or bad PCB layout (like no solid GND plane) may cause the described problem.
Thus we need to see the PCB layout, including ESD path.

Added:
* ESD rating usually refers to signal lines, not power supply lines
* ESD rating usually means what "kills" the device, it does not mean the device does not latch up after an ESD pulse - unless specified this way.

Klaus

 

[FvM]

ESD has limit charge, I agree that it's unlikely to get potential dangerous voltage surge at power pins of assembled devices, presumed the circuit implements usual bypassing.

There's however a general problem with ESD ratings. ICs are usually tested in unpowered state. An ESD event on some pins can cause latchup. If the power supply isn't current limited, the IC will be typically destroyed.

I experienced this problem with an RF transceiver chip of a major manufacturer. A relative small ESD spike < 100 V at the antenna output triggered a latchup. The problem could be only overcome by a current limiting load switch cutting the IC power supply.

 

[dick_freebird]

ESD rating, generally, is for a bare unpowered part. It is
for handling during assembly and test.

There have been developed some equipment-level specs
for things like consumers plugging in HDMI cables while
shuffling feet on carpet. But these have not flowed down
to products generally, only where customers see it to
matter.

What you describe is powered pin induced electrical
latchup. Likely from pushing an ESD diode forward on
a signal pin and injecting substrate currents which
trigger one of the many parasitic SCRs in CMOS technology.

You will see input and tri-stated I/O pin current max
ratings addressing this fault mode, typically 10mA or so
is what basic groundrules for I/O devices will support
with guardrings and spacings (a CMOS input should have
none, so going bigger is generally just a waste of area
to save the really stupid or unlucky from themselves).
The pins also have abs max voltages which your 200V
spike likely violates (unless this is high side supply in a
power management IC, or something like that, rated for
it).

Series resistors and aux clamp diodes may be wanted on
assembly pins that are exposed to long wires, connector
fiddling or externally imposed electrical faults. There may
be pins which can't tolerate that, and need other solutions.

 

[D.A.(Tony)Stewart]

I have this device

My system experienced an ESD event up stream of the 3.3V supply line.

The chip locks up after this event.

The scoping of the power supply lines measured a spike of > 200 volts caused by this event.

The chip is rated for ESD protection >8kV, but unsure if I understand this rating correctly.

How would you specify the ESD event on the supply line?
Microchip defines it as HBM ESD Performance JEDEC Class 3A and this link defines that as 4 to 8 kV.
The HMB= Human body model = 100 pF + 1k? This is a measure of a finger touch area during an arc.

The SCR latchup mode is current-limited on input signal lines with typically 2 stages of R(=10k~50k)+ Schottky dual small signal diodes for the rails. So if the supply drops below the signal voltage by more than the diode drop, an SCR latchup will occur.

So defining your environmental noise events carefully is critical, then solving it is easier. If 200V impulse was injected, how short was the 10:1 probe ground cable ? < 2cm? Otherwise as was already suggested, measurement errors can occur with antenna effects on the probe ground. (typ> 20MHz)

DC Supply Noise should always be measured with AC coupled to 50 Ohm cable to 50 ohm termination for least interference. ( and short semi-rigid coax is best)

Also Long cables dragged on carpets then plugged in may have less than 4kV but at 100 pf/m may have significant Q=CV which is the total discharge. Ideally, you want to have your LAN chip protected connecting a charged cable to a live so additional protection is needed with low pF solid-state clamp diodes. (TVS)

e.g. many sources exist. Here is TI's.

https://www.ti.com/lit/sg/sszb130d/sszb130d.pdf