richeek
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Hi
I have written a verilog code for a processor. It has a program counter. When I am running check design on my top module, I get an unconnected port in PC.
Here is the verilog code of PC:
`timescale 1ns / 1ps
module PC(din, dout, load, countEn, rst);
input[7:0] din;
input load, countEn, rst;
output[7:0] dout;
reg[7:0] dout;
always @(posedge countEn)
begin
if(rst)
dout <= 0;
else if(load)
dout <= din;
else
dout <= dout + 1;
end
endmodule
I descended in the hierarchy and there is a cell B_1 in PC that is unconnected.
The problem is that I am unable to debug why this cell is getting generated at the first place? What is redundant in my code? I am attaching the JPEG image of the generated design schematic of PC.
Any help would be appreciated.
Thanks.
Richeek
I have written a verilog code for a processor. It has a program counter. When I am running check design on my top module, I get an unconnected port in PC.
Here is the verilog code of PC:
`timescale 1ns / 1ps
module PC(din, dout, load, countEn, rst);
input[7:0] din;
input load, countEn, rst;
output[7:0] dout;
reg[7:0] dout;
always @(posedge countEn)
begin
if(rst)
dout <= 0;
else if(load)
dout <= din;
else
dout <= dout + 1;
end
endmodule
I descended in the hierarchy and there is a cell B_1 in PC that is unconnected.
The problem is that I am unable to debug why this cell is getting generated at the first place? What is redundant in my code? I am attaching the JPEG image of the generated design schematic of PC.
Any help would be appreciated.
Thanks.
Richeek