Unable to set loop itierator above 60

[rt900]

Hi all,

I have read through similar posts on this topic however have been unable to find an answer...

I am trying to implement an 8 bit by 8 bit divider without the use of the "/" symbol in verilog. The code I have written compiles, however will only generate the correct answer when the loop iterator is below 60. The code I have written is:


always@(num1,num2)
begin
temp_answer = 8'b0;
k = 0;
temp_num1 = num1;
temp_num2 = num2;
while(k<100)
begin
if(temp_num1>temp_num2)
begin
temp_num1 = temp_num1 - temp_num2;
temp_answer = temp_answer + 1;
end
k=k+1;
end
answer = temp_answer;
end
endmodule


Num1 and num2, are two signed numbers (in two's complement form) entered (on the altera DE2 board) by the user. The code compiles with any k value, however only generates the right answer in the waveform simulator when k < 60. This is a problem as the largest value that can be output is 128 (128/1), therefore i need the loop to perform 128 iterations. I know this isn't efficient at all, however I need to get it working.

Any help would be appreciated,
Thanks

 

[rt900]

I may have been slightly vague in the question above, so let me clarify.

Is there any obvious reason why the code below will output the correct answer when the loop iterator (k) is set to 60, but outputs an X (when using waveform vector simulator) when the loop iterator is set to a higher value than 60?


temp_answer = 8'b0;
k = 0;
while(k<=65)
begin
if(number1>number2)
begin
number1 = number1 - number2;
temp_answer = temp_answer + 1;
end
k = k+1;
end
answer = temp_answer;


Your help would be great,
Thanks

 

[permute]

firstly, that is the worst possible implementation in any language. Try long division.

Secondly, think about hardware. While loops are essentially never used in actual designs because while loops almost never generate small/efficient hardware.

 

[qieda]

Hi,

is k defined as an integer?

Can you try a for loop
integer k;
for ( k = 0; k < 65; k = k + 1 ) begin
...
end


regards

 

[FvM]

Points that are missing in the initial post:
- definition of variables
- explanation of "doesn't compile"

You mentioned an Altera DE2 evaluation board, so the obvious guess is, it doesn't compile because your design exceeds the number of available logic cells in the respective FPGA. Which would validate "the worst possible implementation in any language". A while loop is generating parallel logic, and there will be always an iteration number N where the design exceeds the chip size.

Use a reasonable divider implementation from literature e.g. a bit-serial one, preferably with sequential processing, not a while loop.