ashourism
Newbie level 6
Dear All I am trying to make a two stage OTA for a SC circuit for usage in a pipelined ADC it should possess a minimum GBW of 205 MHz across all corners
however across the ss corner (UMC130rf) the current mirroring ratio get extremely missnmatced that it get multiplied by two from 65u Iss to 120u !
pushing the amplifier input transistors of first stage into extreme linear region thus the gain drops below 0 db! while the min spec is 48db!
However the CMFB loop amplifiers keep its current mirroring ratios!
how is this possible aren't corners variations happen across the whole circuit?
And second does anyone have a suggestion to solve this issue and push back the transistors into saturation?
1. Amplifier in TT State
2. CMFB in TT State
3. Amplifier in SS State
4. CMFB in SS State
you will notice that picture two and four have the same current across corners while one and three don't!
however across the ss corner (UMC130rf) the current mirroring ratio get extremely missnmatced that it get multiplied by two from 65u Iss to 120u !
pushing the amplifier input transistors of first stage into extreme linear region thus the gain drops below 0 db! while the min spec is 48db!
However the CMFB loop amplifiers keep its current mirroring ratios!
how is this possible aren't corners variations happen across the whole circuit?
And second does anyone have a suggestion to solve this issue and push back the transistors into saturation?
1. Amplifier in TT State
2. CMFB in TT State
3. Amplifier in SS State
4. CMFB in SS State
you will notice that picture two and four have the same current across corners while one and three don't!
