two fully differential opamps, different gains, why?

[lhlbluesky]

i have designed two fully differential opamps using tower 0.18um 1.8v/3.3v technology (two stage, folded cascode + common source, with cascode compensation and continueous common feedback), one has dc gain of 108dB,
and the other has dc gain of 98dB (tt corner, pre-simulation); but after the layout extraction, when running layout post-simulation using calibre, i find that, the first opamp has dc gain of 69dB, and the second has only dc gain of 28dB, why?

in layout design, i have considered the basic layour design rules, such as matching of transistor pairs, wide enough wires for current density, the whole symmetric routing etc. i have tried to optimize my layout, but it only improves a little. i'm really confused.

has anyone ever met this problem before? and can anyone give me some advice or suggestion? what is the possible reason? pls help me. thanks all.

 

[erikl]

Re: about opamp gain, pls

Extracted parasitics shouldn't decrease the DC gain. Are you sure your layout equals the schematic? LVS successfully run?

 

[lhlbluesky]

about opamp gain, pls

my LVS is successful and there are no errors, but what is the reason for DC gain decreasing? which factors can cause the decreasing?

 

[erikl]

Re: about opamp gain, pls

I have no idea, lhlbluesky, sorry! I never had such a problem.
I'd try and delete the parasitics from your postLayout netlist (tedious, I know!) and then simulate again. Perhaps then you might find out what's wrong.
Good luck!
erikl

 

[lhlbluesky]

about opamp gain, pls

but how to delete the parasitics from my postLayout netlist, i think this is very difficult, what is your opinion?

 

[erikl]

Re: about opamp gain, pls

Another idea, lhlbluesky:
Did you possibly use RLC extraction? If so, a parasitic R could have been extracted, which wouldn't disturb the LVS (because it's considered parasitic), but quite well could decrease the DC gain (e.g. some high-ohmic connection between nodes in the same well).
Just guessing!

 

[lhlbluesky]

about opamp gain, pls

any other ideas, pls?

Added after 3 minutes:

i didn't use RLC extraction, i use RCC extraction. besides, RLC extraction can decrease the DC gain, why? can you explain more?

 

[erikl]

Re: about opamp gain, pls

but how to delete the parasitics from my postLayout netlist, i think this is very difficult, what is your opinion?

Depends on what type of extraction you have run: If it was just a C extraction, removing the parasitics is relatively simple: just rm all parasitics (or just don't include the parasitics file).
With RLC extraction, the removal would be extremely tedious, as mentioned already. In this case, I'd repeat a C-only extraction and re-simulate, first including the parasitics and check the results.
Good luck!

Added after 8 minutes:

... i use RCC extraction. besides, RLC extraction can decrease the DC gain, why? can you explain more?

I already gave you a hint (above) :

... (e.g. some high-ohmic connection between nodes in the same well).

This could result in a (high-ohmic) short-circuit between nodes, which could decrease the DC gain.
In your case, I'd run another C or CC extraction (without R extraction) and re-simulate (as mentioned before).

 

[lhlbluesky]

about opamp gain, pls

why can high-ohmic contact cause short-circuit between nodes? i think, high-ohmic contact will be considered open-circuit, not short-circuit, ok?

 

[erikl]

Re: about opamp gain, pls

why can high-ohmic contact cause short-circuit between nodes? i think, high-ohmic contact will be considered open-circuit, not short-circuit, ok?

Between 2 (also) high-ohmic nodes, a high-ohmic "short circuit" (parasitic R) can quite well decrease the DC gain, e.g. a parasitic R between the inputs of a differential amplifier, or between the sources of a degenerated common-source pair with separate sources, or between 2 high-ohmic nodes in a folded-cascode pair, or between the outputs of a current source pair ...

Run a CC-only extraction, and you'll find out if a parasitic R is responsible.

 

[lhlbluesky]

about opamp gain, pls

oh, thanks erikl, i will try it.

 

[ankitgarg0312]

Re: about opamp gain, pls

capactive parasitics are not expected to change low frequency gain...
you can extract r-only parasitics and then run simulations on extracted netlist..
i suspect in r-only simulations you will face same issue...

as per my guess may be some resistors in signal paths are changing your bias conditions and some transistior comes out of saturation

For calibre xrc , there are options in gui to change extraction as r , r+c, R+c+CC ....
which tools are u using for extraction??
or u can comments out all of C* in designs

 

[suria3]

Re: about opamp gain, pls

Hi,

It is very weird to see that your post layout and pre-layout gain does changed a lot. Normally, even it change also, it will be of the delta=1dB due to R parasitics. May be i can suggest you to check on this as a basic troubleshoot.

1) Ensure your LVS is clean
2) Are you using the same testbench as used for prelayout?
3) Are you getting the about the same DC voltage at the output of 1st and 2nd stage compared to pre-layout?
4) Make sure the the DC biasing and AC=1 is properly set.

So, if you can ensure those settings works fine, then you move ahead to next troubleshooting on the layout level as what others had suggested.

Good luck,
Suria

 

[lhlbluesky]

about opamp gain, pls

as ankitgarg0312 says, in r-only simulations i face the same issue, the dc gain also decreases a lot, just as RCC simulation. but when i run C+CC simulation, there is no parasitic res, the post-simulation is almost the same as pre-simulation. so, i think it is some parasitic res that causes the issue. however, i tried many ways to improve my layout, it doesn't improve at all. i'm really confused.

besides, i use the fully differential opamp for sc circuit; when presimulation, the whole circuit resolution is 14bit, althrough the dc gain of opamp decreases a lot (from 98dB to 28dB)relative to pre-simulation, the whole circuit resolution for post-simulation can still be 11bit; why? i don't think this is reasonable. 28dB is only 25 times, i don't think the so small dc gain can make the whole circuit reach 11bit resolution in post-simulation. why? can anyone give me some suggestion, pls?

and how to find which parasitic resistor causes the DC gain decreasing in post-simulation or in layout? are there some methods or ways? it's really very urgent, i really need your help. thanks all for reply. thanks.

Added after 1 hours 47 minutes:

besides, i find a zero in post-simulation (AC) response curve. why? what's the reason? can anyone help me about the issue above,pls?

 

[erikl]

Re: about opamp gain, pls

... besides, i use the fully differential opamp for sc circuit; when presimulation, the whole circuit resolution is 14bit, althrough the dc gain of opamp decreases a lot (from 98dB to 28dB)relative to pre-simulation, the whole circuit resolution for post-simulation can still be 11bit; why? i don't think this is reasonable. 28dB is only 25 times, i don't think the so small dc gain can make the whole circuit reach 11bit resolution in post-simulation. why?

The amount of resolution doesn't necessarily depend on the DC gain. It could still be such high. Anyway you should find out, why the DC gain decreases so much.

and how to find which parasitic resistor causes the DC gain decreasing in post-simulation or in layout? are there some methods or ways?

Work through your parasitic R netlist and try to find out some relative high resistor values (in comparison to the normally rather low values of the extracted connection resistors), which possibly could decrease the DC gain. And then find out where they are in the layout.

besides, i find a zero in post-simulation (AC) response curve. why? what's the reason? can anyone help me about the issue above,pls?

A serial RC circuit. This also could give you a hint where such a bad resistor is hiding. A parasitic R in series with a switched cap? Perhaps built-in in the cap itself, because of insufficient plate connections (too few contacts)?

 

[lhlbluesky]

about opamp gain, pls

i use PDK, so, the built-in resistor in cap itself will not exist, ok? and any other ideas?

 

[erikl]

Re: about opamp gain, pls

i use PDK, so, the built-in resistor in cap itself will not exist, ok?

Well, if you think so ...

any other ideas?

Definitely no, from my side!

 

[lhlbluesky]

about opamp gain, pls

why no? PDK can't be changed randomly, ok? how to understand built-in resistor in cap itself in detail?

 

[ankitgarg0312]

about opamp gain, pls

i would suggest to do a grep on your parasitic file for pattern ^R to find out all resistors, redirect it to a file use perl/tcl/awk to get 4th column from that file ( res values) sort them using unix commands.....

verify that all parasitic resistors are in a permissible range ,it may happen that there may be soft connect or virtual connect issue. ( ensure that u have soft connect/virtual connect switches in appropriate usage for lvs)

Added after 5 minutes:

if above things dont helps , then best solutions will be to break problem in smaller peices, start probing main internal nodes, and compare with prelayout nodes ...

e.g. get operating point voltages of nodes in prelayout desings, simlarly get op voltages for post layout nodes and compare them to see is there any particular node having too much variations..

or

probe internal nodes for ac gain pre vs postlayout ..
you will easily figure out the problem....

 

[PaloAlto]

Re: about opamp gain, pls

I think that I know what could be happening here At least I have had the same issue before and also using tower 0.18

OK, first of all, as they say parasitics should not change DC response, so there's something wrong there. I suggest you to do an extraction, but instead of R, C or RC, do an lvs_extract, so what you get is a netlist that should be exactly the same as the one from schematics, compare those two and you will find the problem with the extraction tool.

In my case, the problem was that the lvs uses a trick to save time: It makes groups of transistors and considers them as a block, for instance a NAND gate. In my case, the cascoded current mirrors where extracted as a nand gate, so connection was not check and they were not correctly connected. What needs to be done here is to include a switch. I don't remember the exact name, but it used to be something like "do not connect gates" or something thelike.

Maybe that's not your case, but it is a good idea to create the netlist from layout and compare it with the one extracted from sch.

Good luck!