TSPC(True-Single-Phase-Clock) problem

[shaq]

true single phase clock

Hello everyone,

If Vdd < Vtn+|Vtp| , what kind of phenomenon that we can avoid?

 

[arunragavan]

TSPC .. u can it ture single phase clocked register coz. the circuit employes only on phase of the clock which is clk only and not clk'. this design is entirely different to c(squared)moss design in which both clk and clk' is needed for the operation..

am not sure abt the phenomenon what we can avoid..ur Vt>Vdd!!! lemme check and get back to u..

with regards,

 

[nani]

hi shaq ,
for simple cmos inverter vdd<vtn+vtp will make short circut current zero since either pmos or nmos will be on.but i doubt whether the circuit will work if there is stacking of nmos or pmos(as in tspc) with this condition