Troubles with TetraMAX test patterns

[TelpDmtr]

Hello. I have problems in understanding patterns, generated by TetraMax ATPG. I have simple circuits (from ISCAS benchmark) with full-scan DFT. And when I dive into patterns (.wgl or .stil) I see some strange things. 90% is predictable and clear to me:

1. scan_select is set to "1" (we are in scan shift mode).
2. we set up register values in the first clock.
3. we set scan_select to "0" (we are looking into combinational circuit outputs), and capture the response in the second clock.

Now to the problem: in rare cases in the third step scan_select remains "1". It means that we don't capture values from combinational circuit, but loading new value instead of it! Why TetraMAX does it? It makes no sense. Doing this, we just load patterns several times without any feedback from the circuit.

If you have any ideas or suggestions - please let me know. Thank you!

 

[kungchuking]

Hi. Actually it's hard to tell why the waveform looks like this without further information about your scan architecture (e.g. how many scan chain? How long each of them etc). I don't think the first diagram corresponds with the second one.

Did you stitch the scan chain yourself?

Since you mentioned "2. we set up register values in the first clock". You are assuming you have only a single flop in your chain. The number of clock cycles needed to setup the circuit depends on the length of the scan chain.

In my opinion, "in rare cases in the third step scan_select remains 1", because the scan chain has more than 1 register in it. While for the first two "normal cases", maybe the circuit want to preload some values into the scan chain (e.g. maybe you have a reset synchronizer there). Many possibilities ...

Thank you.

 

[TelpDmtr]

Thank you for your reply! I'll try to clarify some issues.

Hi. Actually it's hard to tell why the waveform looks like this without further information about your scan architecture (e.g. how many scan chain? How long each of them etc). I don't think the first diagram corresponds with the second one.

Did you stitch the scan chain yourself?

It is the simplest possible circuit - s27. It has 1 combinational block - only 9 logic cells; 1 scan chain with 3 simplest scan flip-flops without any set|reset. Only D, Q, NQ, CLK, SI, SE. Scan chain was generated by Synopsys DFT Compiler. All DRC checks were passed. I examined this circuit very thoroughly, and there are no surprises there...

Since you mentioned "2. we set up register values in the first clock". You are assuming you have only a single flop in your chain. The number of clock cycles needed to setup the circuit depends on the length of the scan chain.

I realize your misunderstanding. Actually it was surprising for me too, but in the .stil and .wgl waveform files from TetraMAX, you won't find many clock cycles for loading/unloading data from scanchain. Instead, there is only one clock cycle to load all the data into the registers. Apparently for these files they omit this long procedure, thereby reducing the file and waveform size. It seems to me that later on, all these effects are taken into account when translating to files for ATE.

In my opinion, "in rare cases in the third step scan_select remains 1", because the scan chain has more than 1 register in it. While for the first two "normal cases", maybe the circuit want to preload some values into the scan chain (e.g. maybe you have a reset synchronizer there). Many possibilities ...

Thank you.

It is still confusing to me, so if you have any ideas regarding this case - I'll be very grateful. If u need more details - I can provide it. By the way, here, for example, I use a small s27 circuit, but this bug appears on other circuits as well. It must be some reason for this "extra" load operation. I can't believe that TetraMax has bugs. (I checked 2015 and 2016 versions).

 

[kungchuking]

I believe that TetraMax doesn't have bugs. If you could provide me wit the following files:
1) Netlist (BTW, What's the library you are using).
2) synthesis, dft, and ATPG scripts
3) .stil and .wgil
4) waveform (.vcd or .fsdb)
... I would be very happy to look into it.
Thank you.

 

[TelpDmtr]

I believe that TetraMax doesn't have bugs. If you could provide me wit the following files:
1) Netlist (BTW, What's the library you are using).
2) synthesis, dft, and ATPG scripts
3) .stil and .wgil
4) waveform (.vcd or .fsdb)
... I would be very happy to look into it.
Thank you.

I've collected all the data, that I have. Netlist, schematic, scripts, patterns and Verilog testbench. We use a simple handmade library with basic 2-input gates and DFF/SDFF without any set|reset nodes. I will be glad for any tips and thoughts. Thank you for your assistance.

https://drive.google.com/open?id=1n3vtghotjvpEuMSGfV4kFBcc4XCu62ak

 

[kungchuking]

You are running the simulation in parallel mode, the testbench created by TetraMAX has multiple entry points:

I believe the following waveform is similar to the one you posted on your first post:

Notice that you were running the simulation at parallel mode (e.g. you didn't specify any option when running the testbench). In parallel mode, the testbench will force the patterns directly into each SDFF.

If you want to run at serial mode, you can issue the following command:
ncverilog +access+rw +define+tmax_fsdb +tmax_serial=9 +tmax_msg=9 -f s27_scan.f
Note: you have total 9 patterns.

If you succeed, your output log should look like the following:


... and your waveform should look like the following:


I believe that answers your question.

 

[TelpDmtr]

You are running the simulation in parallel mode, the testbench created by TetraMAX has multiple entry points:
View attachment 158159
I believe the following waveform is similar to the one you posted on your first post:
View attachment 158160
Notice that you were running the simulation at parallel mode (e.g. you didn't specify any option when running the testbench). In parallel mode, the testbench will force the patterns directly into each SDFF.

If you want to run at serial mode, you can issue the following command:
ncverilog +access+rw +define+tmax_fsdb +tmax_serial=9 +tmax_msg=9 -f s27_scan.f
Note: you have total 9 patterns.

If you succeed, your output log should look like the following:
View attachment 158161

... and your waveform should look like the following:
View attachment 158162

I believe that answers your question.

Thank you very much for your participation. It already helped a lot. But unfortunately, the main question still remains. Let me clarify my point:

1. Is it true that the main procedure goes in two steps: (1) load|unload data (2) capture the response from the combinational circuit?
2. Is that correct that we are capturing our data only when signal "test_se" = 0?
3. If the above two statements are correct - why there are places in the waveform where we load data and then DON'T capture any response?

I've attached your waveform from the previous post and marked parts where I have my concerns.


Thanks again!

 

[kungchuking]

It is true that the whole test process (excluding the maybe the initial test setup follows a regular load/unload -> measure/capture pattern.

However, test_se is (mostly) not always asserted in measure/capture cycles. In measure capture cycles, DFT compiler treats the scan-enable signal like any other parallel input. This is important, since sometimes the captured data can be from the scan path rather than the functional path. Treating the scan-enable signal as a parallel input allows the scan logic and clock logic to be included in the fault list. If you exclude them, you won’t be able to test for the possible failures of those nodes (e.g. your test coverage won’t be 100% in your case).

Thank you.