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Transistor Properties in Layout simulation

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Bakez

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Im using Spectre/Virtuoso to simulate the layout for a small logic circuit vs its schematic. When I view the netlist it displays several transistor properties, but I have no idea what some of them are:

Code:
tsmc18dN w=360.0n l=180.0n as=1.62e-13 \
ad=1.62e-13 ps=1.62u pd=1.62u m=1 region=sat

Obviously W and L are width and length, but what are the others: AS, AD, PS, PD and M?

Added after 7 minutes:

These values appear to be differ between my transistors in the layout vs schematic, but all the W and L match
 

Bakez said:
... what are the others: AS, AD, PS, PD and M?
AS: Source Area
AD: Drain Area
PS: Source Perimeter
PD: Drain Perimeter
M: Multiplicity = number of parallel transistors with W/L
region: in which part of its characteristic the transistor is working

Bakez said:
Added after 7 minutes:
These values appear to be differ between my transistors in the layout vs schematic, but all the W and L match
That's enough for your LVS being clean!
 

My layout is actually faster than the schematic even with all the parasitic capacitances added in... it has to be to do with those 4 values
 

Bakez said:
tsmc18dN w=360.0n l=180.0n as=1.62e-13 ad=1.62e-13 ps=1.62u pd=1.62u m=1 region=sat
The areas seem ok (drain/source area length=450n); the perimeter values, however, are strange. Usually, perimeter=(w + 2*(area length))=1.26µ , not 1.62µ .

Bakez said:
My layout is actually faster than the schematic even with all the parasitic capacitances added in... it has to be to do with those 4 values
Weird. Can you post one - or a few - MOSFET comparison lines from the schematic & layout netlists? (Indicate, which is which.)
 

Hi, thanks for your help

Schematic:

**broken link removed**

Extracted:
**broken link removed**
 
Last edited by a moderator:

erikl said:
The areas seem ok (drain/source area length=450n); the perimeter values, however, are strange. Usually, perimeter=(w + 2*(area length))=1.26µ , not 1.62µ .

surely 2*(area length + width) = 2*(450 + 360) = 1.62 which is correct? Perimeter must have 2 lengths and widths.

Keith
 

keith1200rs said:
surely 2*(area length + width) = 2*(450 + 360) = 1.62 which is correct? Perimeter must have 2 lengths and widths.
Keith
Hello Keith,
in most cases, perimeter pd = drain perimeter not adjacent to the poly gate, i.e. 2 lengths and only 1 width, s. my posting from Thu, 16 Apr 2009 19:55 here **broken link removed**. Depends on the extraction rules, of course. The BSIM standard, however, expects the perimeter values don't include the gate-edge width, see e.g. the BSIM 4.6.2 manual, p. 133: "Whether PS/PD (when given) includes the gate-edge perimeter".
 
Last edited by a moderator:

I am with erikl about the perimeter which does not count the gate edge. The discrepancy betwen perimeter=(w + 2*(area length)) and the real parameters extracted by LVS commands is probably because it is a dog bone. You have to see the real layout and know how to calculate the perimeter. The attached file is for your reference.
 

Hi erikl,

is there a doc which expain the physical reason not to take perimeter diode into account?

To my understanding for a 1-D channel analysis you still assume that there is a AC current in the corners of drain/source diffusion depletion zones to substrate.

For small devices e.g. the channel length modulation impacted by the lenght variation of depletion zone is 2-D calculated. But still of the substrate potential change there is an AC depletion current form the diode capacitance which does not go into channel.

Any docs?
 

rfsystem said:
Hi erikl,

is there a doc which expain the physical reason not to take perimeter diode into account?

Yes, I would be interested as well. I found one reference in an early BSIM3 document which stated

"We do need to support two definitions of the parameters PS and PD, one including the gate
edge perimeter and one excluding the gate edge"

but nothing that explains why it is excluded. While some perimeter leakage/capacitance along the gate will be to the channel not substrate, due to the depth of the drain diffusion I assume there is also some perimeter leakage and capacitance to substrate along the gate width.

Keith.
 

So if because of simplication of parasitic calculation there is either to take the edge or to skip. For non-LDD rembering some device simulations I think much more than 50% of the depeletion current goes to the substrate. So taken the 50% argument that match more cases which I found which calculate pd=2*(W+Ldif).

For LDD this could be different. Then there are 2 diode types and a significant lateral parasitic resistor.
 

rfsystem said:
Hi erikl,

is there a doc which explains the physical reason not to take perimeter diode into account?
I didn't find any doc on this, sorry. IMHO this is arranged because the gate properties already take account of the corresponding quantities re. capacitance and leakage. But this is my own explanation and may not be correct.

keith said:
I found one reference in an early BSIM3 document which stated

"We do need to support two definitions of the parameters PS and PD, one including the gate edge perimeter and one excluding the gate edge"
Right. BSIM 4.6 differentiates between both definitions: PERMOD=0 means total perimeter, PERMOD=1 means perimeter excluding the gate edge (sometimes also called "periphery" instead of "perimeter").
 

The story is simple:

The doc is here:

**broken link removed**

Page 101 (11.13)

The diffusion/gate edge is substracted because in the hole calculation for the diffusion diode cap is added by a sidewall cap which allows more flexibility and accuracy representing the LDD diodes which have lower caps

https://obrazki.elektroda.pl/44_1269438637.png
 
Last edited by a moderator:

I think I have found the problem:

Here is a picture of the pFETs from my layout:

**broken link removed**

I've added rulers to show dimensions.

And here is the netlist for the layout during simulation:

**broken link removed**

It takes a while to work out and is quite difficult to explain here but we can see that the simulator has infact used perimeter=(w + 2*(area length)) for the source and drain at either ends, but for the 2 centre source/drain sections the simulator has just used PERIMETER = LENGTH, not even taking into account both sides that arent adjacent to the poly :?:

This must be why my layout is faster than the schematic... but why has it done this?
 
Last edited by a moderator:

Bakez said:
... we can see that the simulator has in fact used perimeter=(w + 2*(area length)) for the source and drain at either ends, but for the 2 centre source/drain sections the simulator has just used PERIMETER = LENGTH, not even taking into account both sides that aren't adjacent to the poly :?:
... but why has it done this?
I guess because this perimeter value is used for both adjacent transistors. By using PERIMETER = 1*LENGTH the corresponding capacitance/leakage values are equitably divided between both transistors. Seems like intelligent extraction!

Bakez said:
This must be why my layout is faster than the schematic
Yes, I think so. The schematic isn't aware of transistor chaining in layout.

Thank you for your feedback, Bakez!

Added after 10 minutes:

rfsystem said:
The doc is here:
**broken link removed**
Page 101 (11.13)
The diffusion/gate edge is substracted because in the whole calculation for the diffusion diode cap is added by a sidewall cap which allows more flexibility and accuracy representing the LDD diodes which have lower caps
Thanks a lot, rfsystem! Didn't find it myself (even if perimeter appears on that page). Shame on me! :-(
 
Last edited by a moderator:

    Bakez

    Points: 2
    Helpful Answer Positive Rating
erikl said:
I guess because this perimeter value is used for both adjacent transistors. By using PERIMETER = 1*LENGTH the corresponding capacitance/leakage values are equitably divided between both transistors. Seems like intelligent extraction!
Took me a few reads to understand what you were saying here, but it all seems so simple now.

Thanks for the help
 

Bakez,

the posts above are only related to the model calculation which take the netlist data. But as I take a look at your numbers ther are discrepancies.


It is not easy to follow the extractred netlist but I grasp the \+4 and the \+3 PMOS which are connected to vdd!

\+4 w=0.72 l=0.18 ps ps=0.675 pd=0.63
\+3 w=0.72 l=0.18 ps ps=1.71 pd=0.675

Because the extracted does not unique identify source or drain and do not plot the extracted view with sufficient zoomed device I can only assume that the

ps=0.675 from \+4

and

pd=0.675 from \+3

is the diffusion region cennected to vdd!

The golden rule for extraction w/o modelling features for shared diffusion is to calculated area and perimeter for the total shared area and then divide that even between attached device.

There are some details here. Only device with shared diffusion, not shared nets are belonging to thsi groups. Second even distribution is also the case for uneven dimensions.

Taking this rule:

A(shared)=0.675*0.72=0.486
P(shared)=2*(0.675+0.72)=2.79

So dividing P(shared) over two PMOS should give 1.395 not 0.675!

That is a big discrepance which I could not explain by some sizing operations. And to be clear not taken into account the gate edge is only a model feature and the capacitance is not skipped but substituted by another cap.

I think the extraction rules are wrong
 

rfsystem said:
There are some details here. Only device with shared diffusion, not shared nets are belonging to thsi groups. Second even distribution is also the case for uneven dimensions.

Taking this rule:

A(shared)=0.675*0.72=0.486
P(shared)=2*(0.675+0.72)=2.79

So dividing P(shared) over two PMOS should give 1.395 not 0.675!

That is a big discrepance which I could not explain by some sizing operations. And to be clear not taken into account the gate edge is only a model feature and the capacitance is not skipped but substituted by another cap.

I think the extraction rules are wrong
I understand what your are saying, but if we were to be consistent with how the perimeter was calculated other 2 diffusion regions at either end (ie the perimeter not adjacent to the poly) - then the P(shared) will infact be = 2*0.675, and therefore over the two pMOS will give 0.675.
 

I think I go with rfsystem. The following commands are copied from the website of Mentor and it is probably helpful.

DEVICE mn gate gate sd sd [
PROPERTY W L AS AD PS PD ...//others
... //other calculations such as W and L...
AS = area(S)
AD = area(D)
PS = perimeter(S)
PD = perimeter(D)
if ( AS == 0 ) {
AD = area(D) / 2
AS = AD
PD = perimeter(D) / 2
PS = PD
}
if ( AD == 0 ) {
AS = area(S) / 2
AD = AS
PS = perimeter(S) / 2
PD = PS
}
...
]
METHOD B:
-------------
DEVICE mn gate gate sd sd [
PROPERTY W L AS AD PS PD ...//others
... //other calculations such as W and L...
IF (pin_net (D) == pin_net (S)) {
AD = area(sd) / 2
AS = AD
PD = perimeter(sd) / 2
PS = PD
} else {
AS = area(sd)
AD = area(sd)
PS = perimeter(sd)
PD = perimeter(sd)
// note that the above lines use pin layers (sd) instead of pin names (S, D)
// this is because you do not know which pin will receive the actual area, and
which
// will receive the zero area.
 

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