Transistor geometric information from Cadence

[tm.torabi]

Hi,
I have a Pcell and I need the geometric information of the tiles shown in the next figure. I have the location of the terminals(S,D and G) but not the mentioned tiles.
Is there any format in Cadence could give me such information?

 

[kemiyun]

Can you explain what you need more clearly please. What tiles? Do you mean M1 rules? Then you should check your PDK docs.

 

[tm.torabi]

Hi,
I want to route a circuit by my algorithm. So, I need the (x,y) location of transistor terminal pins. That is to say I need to connect D,S and G of the transistors. Also, I found that the only way to access those pins are the mentioned M1 tiles for D,S anf G.
Thus, I need a stream format which can report those tiles of a layout.

Please let me know if any more information in needed.

Thanks

 

[kemiyun]

Do you need the relative positions of pins, is that all? You can do that in SKILL and write the output in a file to be read using whatever tool you are using.

Similarly you can use SKILL to get information about positions of metals if that's what you wish.

And last you can use SKILL to read from a file that you created using whatever tool you are using to make the routing.

But SKILL is a somewhat different language and it might take a while to learn it, perhaps someone else can offer a better way. Also I'm not very sure I understand the question very well either.

 

[tm.torabi]

Hi,
Thank you for your reply.
I think SKILL is a good choice.