Transient logic of zener level shifter

[yefj]

Hello, In the circuit bellow a Level shifter was made using Zenner diode.
However as you can see it drops only at the second pulse to the desired value.
Is there a way to make it do the level shifting from the first pulse?
Thanks.

 

[KlausST]

Hi,

.. you call it Zener shifter...

but indeed the "shifting" is done by the capacitor. The Zener is just the "voltage limiter".
The capacitor needs to be charged to the desired level.

It is not perfect, because it is not useful for higher current and not useful for very low frequencies.
And as you already know it needs to be "initialized". This initialization is only possible for known input state and needs extra circuit.

Extra parts ... while not perfect.
So why not use a dedicated level shifter, an optocoupler, a digital isolator, an analog switch, or similar?

****
Especially when you want to (worldwide) share a schematic I vote for using standard symbols. A box with numbers "1" and "2" could be anything.
And if you do a simulation, then try to do it realistically .. with a load.

Klaus

 

[danadakk]

Is you zener in backwards polarity, so its just clamping at .7V ?

The design is seeing the differentiator action of a RC to a square wave. The
peak generated by the C + R (100 ohm) + R (dynamic R Zener).

As Klaus points out you really have a clamp circuit, not a shifter.

Why do yiou have the Capacitor ? Describe goal of circuit, Vin range, frequency,
Vclamp and its needed accuracy.....load on circuit output.....


Regards, Dana.

 

[D.A.(Tony)Stewart]

Hello, In the circuit bellow a Level shifter was made using Zenner diode.
However as you can see it drops only at the second pulse to the desired value.
Is there a way to make it do the level shifting from the first pulse?
Thanks.
View attachment 190114

Holy cow. This is a question techs. might ask in 101 electronics.
The diode never reaches reverse breakdown voltage and acts a simple passive +ve clamp circuit.
In the diode clamp driven by a series RC + signal 0 to 3.3V you expect the diode to have two states, ON & OFF with a series resistance you can estimate for each using the datasheet. The resistance can be estimated by V/I for forward and reverse biased from the datasheet, which I expect you can read and interpolate for 3.3V.

What do you estimate for the diode Rs with a fixed voltage drop of (3.3-0.8)/ 100 ohms= I being the diode current?

All TV's take the AC coupled video signal and then clamp the "back porch" after negative sync tip using an active pulse to short circuit the load for 100 ns when the output is expected to be 0V. This serves as the video 0% IRE or "black" level reference. This is an active clamp as opposed to the passive diode clamp using a low C[pF] FET with say <1 Ohm.

Since video signals use 75 Ohm impedance and using 5 T decay times for a low steady-state (SS) error ...
Can you estimate the resistance of the switch in the ON state? R=T/C and choose C such that the output does not decay more than 1% during the Hsync period of video of 15 ms with an estimate leakage current in the OFF state of say 1uA?

Can you think of a DC coupled circuit that has a negative non-inverting level shifter function? (using a transistor with a negative Vss load)
Can you think of a way to shift the load so the negative output is no 0V and the load is now +ve so your circuit runs off a single +ve supply? is it floating?

 

[crutschow]

s there a way to make it do the level shifting from the first pulse?

You can use a resistive divider at the output of the capacitor from a V- supply to ground to set the DC average level at the value that occurs when the circuit is operating.

 

[D.A.(Tony)Stewart]

You can use a resistive divider at the output of the capacitor from a V- supply to ground to set the DC average level at the value that occurs when the circuit is operating.

He is obviously resisting to use a negative supply and also if he wants to drive FET gate (this is getting old) he needs at least a 2.5x Vgs(th) =Vgs swing. Thus attenuation is not a good side effect.

--- Updated Apr 16, 2024 ---

Holy cow. This is a question techs. might ask in 101 electronics.
The diode never reaches reverse breakdown voltage and acts a simple passive +ve clamp circuit.
In the diode clamp driven by a series RC + signal 0 to 3.3V you expect the diode to have two states, ON & OFF with a series resistance you can estimate for each using the datasheet. The resistance can be estimated by V/I for forward and reverse biased from the datasheet, which I expect you can read and interpolate for 3.3V.

View attachment 190137



What do you estimate for the diode Rs with a fixed voltage drop of (3.3-0.8)/ 100 ohms= I being the diode current?

All TV's take the AC coupled video signal and then clamp the "back porch" after negative sync tip using an active pulse to short circuit the load for 100 ns when the output is expected to be 0V. This serves as the video 0% IRE or "black" level reference. This is an active clamp as opposed to the passive diode clamp using a low C[pF] FET with say <1 Ohm.

Since video signals use 75 Ohm impedance and using 5 T decay times for a low steady-state (SS) error ...
Can you estimate the resistance of the switch in the ON state? R=T/C and choose C such that the output does not decay more than 1% during the Hsync period of video of 15 ms with an estimate leakage current in the OFF state of say 1uA?

Can you think of a DC coupled circuit that has a negative non-inverting level shifter function? (using a transistor with a negative Vss load)
Can you think of a way to shift the load so the negative output is no 0V and the load is now +ve so your circuit runs off a single +ve supply? is it floating?

Capiche? any questions?

 

[crutschow]

He is obviously resisting to use a negative supply

I answered his question.
I see no particular basis for that assumption.

 

[D.A.(Tony)Stewart]

His questions are more focused (myopic) and missing all the requirements.

It was hinted on March 9th with a 10 GHz Pch power FET in a 300W RF Amp that needs a negative gate voltage pulse, which must be controlled by drain current sensing.

A common base PNP can level shift a uC logic level to negative swing load resistor with a diode clamp.

 

[yefj]

Hello Tony,Could you show an example so i could simulate such diode PNP clamp?
Thanks.

"A common base PNP can level shift a uC logic level to negative swing load resistor with a diode clamp."

--- Updated Apr 16, 2024 ---

Hi,

.. you call it Zener shifter...

but indeed the "shifting" is done by the capacitor. The Zener is just the "voltage limiter".
The capacitor needs to be charged to the desired level.

It is not perfect, because it is not useful for higher current and not useful for very low frequencies.
And as you already know it needs to be "initialized". This initialization is only possible for known input state and needs extra circuit.

Extra parts ... while not perfect.
So why not use a dedicated level shifter, an optocoupler, a digital isolator, an analog switch, or similar?

****
Especially when you want to (worldwide) share a schematic I vote for using standard symbols. A box with numbers "1" and "2" could be anything.
And if you do a simulation, then try to do it realistically .. with a load.

Klaus

Hello Klaus, In the circuit below,I didnt have this transient phenomena.
From the first pulse output reacted exactly as the other pulses.
the box is imported spice file of zenner diode with 3.6V reverese voltage.
pin one is anode pin 2 is cathode.
Why in one configuration it takes two pulses to reach the desired result while in the clamp circuit below i get the desired result from the first pulse?
Why the capacitor is charge and functioning from the first pulse in the circuit below while on the circuit of the first post it takes two pulses to charge?

Thanks.

 

[D.A.(Tony)Stewart]

No specs given ,so best guess CB to CC.
- some parasitic RLC parts added.

 

[KlausST]

Hi

In the circuit below,I didnt have this transient phenomena.
From the first pulse output reacted exactly as the other pulses.

Your statement is absolutely wrong.

While the circuit of post#1 shows to be "adjusted" within one clcock cycle ... your new circuit never gets to the same performance.

When you see the input it is peak-to-peak of 3.3V in post#1 ... and the output also gets almost 3.3V pp.

Now to you your circuit of post#9:
You also have a 3.3V pp input voltage (why these unrealistic 0.7V / 4.0V levels??) .. now look at te output: it is nowhere near 3.3V pp!!
It´s rather 1.4Vpp (Flat part to flat part).

It´s a complete differetn circuit with complete different function and levels. It´s a riddle why you modified it this way.

***

You did not state how you expect the circuit to work.
I don´t like guessing when doing electronic designs.

Klaus