TML vs TML-Zero Port Calibration in Momentum

[doctorworm]

Hi Everyone,

I'm designing a MMIC PA at ~40 GHz and have noticed that the EM simulation results for my matching networks show VERY different results when switching between TML and TML-zero ports.

I've always been told that TML ports are the best option if they're on the boundary of the structure (i.e. no other structure in the layout extends past them), otherwise TML-zero should be used. I've also found that a stand-alone element like a MIM cap, directional coupler, transformer or a length of line etc. closely resembles the schematic equivalent if TML ports are used... in my mind, "TML = good, TML-zero = not-so-good".

TML-zero ports appear to make 50 Ohm lines look capacitive on the Smith chart, and MIM cap exhibit a much lower self-resonances, so I generally don't trust them.

So... after designing a matching network using TML ports at the input (drain manifolds) and output (gate manifolds), I had to change the output ports to TML-zero, as other structures extended beyond the TML ports and this totally messed up the response. We're talking total mismatch and about half the bandwidth lost. No amount of +/- MLIN length or lumped L/C value can bring me back to me TML-port response so I don't know what the change in port calibration is doing to my circuit and, more importantly, whether using TML ports at the transistor gate/drain manifolds was the correct thing to do in the first place.

Any advice???

 

[volker@muehlhaus]

GaAs or Silicon? What MMIC technology (type) is this?

Long ago, I had evaluated different port calibration methods for SiGe technology with lossy substrates (2 S/m to 5 S/m) and found that calibrates hurts more than it helps. These TML calibrations rely on lines with "regular" behaviour, with doubled phase for doubled line length, and simple lines over Silicon with substrate backside as global ground = return path didn't behave like that in my tests.

My conclusion was to switch OFF port calibration for this type of technology.

 

[doctorworm]

Thanks for the reply!

It's actually GaN-on-SiC - 3 mil substrate thickness, with a <1 um layer of SiN just below the metal layers... so not the lossiest substrate.

The confusing part for me is that stand-alone components and 50 Ohm lines are a much better fit to the PDK models using TML ports. I did several experiments a while ago and the TML-zero/direct 50 Ohm lines came out too capacitive, and if I simulated a MIM cap with TML-zero/direct ports, the SRF was much much lower than it should be (although the low-frequency C was the same. The foundry recommends TML ports for cap simulations too, so there's a lot of confusion for me right now. It seems like TML ports are good for some things but not for others.

Do you think what I'm describing is the same type of behaviour you saw in your simulations?

 

[volker@muehlhaus]

No, what you observe must be a different effect. My issue is related to lossy Silicon and using backside metalization for TML (which is not used as circuit ground).

I have no experience with Momentum calibration on GaAs substrates, so I can't confirm or explain what is going on in your case.