Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Tlock for CLKDLL in simulation.

Status
Not open for further replies.
A

ahmadagha23

Guest
Hi
I simulated a CLKDLL component individually(as top module) for 20MHz input and Tlock was achieved 313 ns; Then I simulated this CLKDLL while it was connected to other components and Tlock was achieved 820ns. Do you know why?
Regards
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top