timing violation netlist simulation

[l.chelini]

Hello guys,

I have a synthesized netlist at 1GHz (STA does not report any violation). However, when I am simulating the netlist (at 1GHz) I am getting: Warning! Timing Violation.
I think there is a problem in my testbench, but I am not able to figure it out.
The testbench used is the following:

begin
  reset <= '1';
  wait for 10 ns;
  reset <= '0';
  while(index_line < Size_test_vectors) loop
    wait until clock'event and clock='1';
    #assign to input
    Xin <= input_vector(index_line);
    #print on a file some info.
    index_line := index_line + 1;
  end loop;
....

Thanks in advance.

 

[Akanimo]

Hi I.chelini,

I may not be right but in your testbench, I would say you change the following line

    ...
    index_line := index_line + 1;
    ...

to

...
index_line <= index_line + 1;
...

so that you have a 'registered' result of index_line to reference for the less-than operation.

 

[ThisIsNotSam]

Hello guys,

I have a synthesized netlist at 1GHz (STA does not report any violation). However, when I am simulating the netlist (at 1GHz) I am getting: Warning! Timing Violation.
I think there is a problem in my testbench, but I am not able to figure it out.
The testbench used is the following:

begin
  reset <= '1';
  wait for 10 ns;
  reset <= '0';
  while(index_line < Size_test_vectors) loop
    wait until clock'event and clock='1';
    #assign to input
    Xin <= input_vector(index_line);
    #print on a file some info.
    index_line := index_line + 1;
  end loop;
....

Thanks in advance.

I think you are seeing clock and data switching at the same time, causing hold violations

 

[Akanimo]

Hi,

Another thing you could check is the timing resolution set in your simulator.

There may be an oversight there.

The resolution may be too big compared with your clock signal.

 

[ads-ee]

I think you are seeing clock and data switching at the same time, causing hold violations

Yeah, you have nothing in the testbench that would emulate the delays that occur on the ASIC inputs/outputs to match what was used for constraining the design. So I can easily believe you would have problems simulating the netlist.