irum4
Member level 3
The device on two FPGA is developed. For each of FPGA time simulation is made. And whether it is possible to write the testbench and to carry out time simulation for the circuit in Aldec or ModelSim, using time models FPGA (time_sim.vhd and time_sim.sdf)? For example: for one FPGA
asim TIMING_FOR_proj_top -sdftyp /UUT = ...\time_sim.sdf
And how will be for two FPGA?
asim TIMING_FOR_proj_top -sdftyp /UUT = ...\time_sim.sdf
And how will be for two FPGA?