achaleus
Member level 5
While doing CDC, I am using 3 flop synchronizer from slow clock(100MHz) to fast clock(250MHz).
It is reporting timing not met as (I am using xilinx 14.7 for synthesis)
Source Clock: clk_100 rising at 10.000ns
Destination Clock: user_clk rising at 12.000ns
but actually it should report
Source Clock: clk_125 rising at 10.000ns
Destination Clock: user_clk rising at 4.000ns
so, what thing do I need to modify in UCF.
Vinay
It is reporting timing not met as (I am using xilinx 14.7 for synthesis)
Source Clock: clk_100 rising at 10.000ns
Destination Clock: user_clk rising at 12.000ns
but actually it should report
Source Clock: clk_125 rising at 10.000ns
Destination Clock: user_clk rising at 4.000ns
so, what thing do I need to modify in UCF.
Vinay