Timing loop problem with: assign mux_a=(en) ? b : mux_a;

[seu_noop]

when i synthesis the design, DC reports that there is a timing loop,
it was caused by the following code
assign mux_a = (en) ? b : mux_a;

This is the combination logic loop? Should I change my rtl code?

 

[megastar007]

Re: timing loop

you should break the loop by putting FF.