Timing Issue

[Sarathjaladi]

I have an FPGA design which contains a multiple counters. There is a state machine which is controlled based on these counters. I am referring this counter register at multiple locations in code. There are timing errors from counter register to output port paritcularly for registers which I have reffered more. The fanout of these signals are 23. How to remove this timing errors.

 

[KlausST]

Hi,

Maybe the problem is in line #23 of your code.

Honestly, how can we help you if you don't show what you have done?

If you need help, please post your code. (Press the [insert code] button)

Klaus

 

[FvM]

As stated, we know effectively nothing about your design. Specifically I would ask:
- Are counters and state-machines following a state-of-the-art synchronous design methodology or e.g. implementing dubious ripple clocks?
- How do you constrain output ports?