Timing Diagram -> VHDL

[Git]

Is there a program that will let you create or load a timing diagram and then save VHDL - i don't mean test bench vhdl, but the vhdl to create the outputs in the td from the inputs in the td ?

Git

 

[r_e_m_y]

I'm afraid you will be obliged to code it by yourself

 

[tlp71@hotmail.com]

if you use integrated development tools , as xilinx, you have a tool that graphically can create a waweform and after save it as vhdl stimulus.
Bye.

 

[DonnaMitchell]

SynaptiCAD's WaveFormer Pro can sorta do this. You can create a timing diagram by drawing waveforms and by writing Boolean equations to describe the waveforms. When exporting to VHDL, the drawn waveforms will look like test bench code. But the waveforms with Boolean equations will look like VHDL gate level code. For more information you can check out their web site at WaveFormer Pro main page

 

[Git]

Thanks Donna, but if you look closer you will see you are 7 years too late

Git