timing constraints in multipliers

[samiksha]

latch multiplier

hi. i'm doing comparison of booth, wallace nd their combination i.e booth encoded wallace tree multiplier in veriog. i'm over wid the coding nd then wid synthesis. in synthesis i calculated the combinatiiomal delay of all three for the comparison purpose. nd getting least for biooth encoded wallace tree multiplier. kindly suggest me what shud i do next to proceed. suggest if something new can be added to this project. waiting for the valuable suggestions
thanku

 

[Nikolai]

Area could be the next point of comparison. Also check whether the multipliers are pipelined or not.

 

[samiksha]

Thanks for replying to my question. bt the point is multipliers are not pipelined.. nd wht abt the timing constraints? how we can check that?

 

[kalyansrinivas]

Hi its not only the frequency (combinational delay) but you should also take latency into consideration since a multiplier working at a good freq may have more latency and may result in poor throughput.

 

[samiksha]

Thanx for a quick response. Bt i have nt added clk in my major block. If i take into account the clock. the result i'm getting after synthesis is that only the setup nd hold time of the whole unit. nt the combinational dely. Actually i'm new to Xilinx also. i'm learning that also side by side. So cud u help me out in this? I mean how to proceed? Waiting for a positive response.

 

[kalyansrinivas]

Hi after running the post place & route open the timing analyzer and load the .ncd file and .pcf file generated by running the placenroute than u can see each and every path with combo dealy setup hold for a specified clock freq. To analyze more paths set the properties in Analyze timing simulation model to verbose report and give the number of paths .

You shold have a clock else you cannot comment on freq of operation

 

[samiksha]

hi
Again Thanku for a quick reply. i have added clk in my module then i synthesised nd place &route the design. loaded both the files . Then i checked aynchronous delay report nd clock region repot.
the report i'm getting shows that there are 20 worst net delays. in synthesis report i'm gettig
Minimum input arrival time before clock: 2.327ns
Maximum output required time after clock: 27.026ns
Maximum combinational path delay: No path found
so can u tell me is it ok or shud i modify my code?

 

[kalyansrinivas]

Latch the inputs to the multiplier using a f-flop
(use an always@(posedge clk)) and also latch the outputs of multiplier using clk (always@(ppsedge clk)) .Now the entire multiplier you designed is between two sets of registers. now if you specify a clock freq using ucf than Xilinx ise will report the timing delay for the combo path between these register sets

 

[samiksha]

hi. i'm not getting the combinational delay of the circuit bt the benefit i got by using this latch is that the dely has been reduced from 27 to 20 ns.
here r the results i'm getting after synthesis.
Minimum period: 20.138ns (Maximum Frequency: 49.657MHz)
Minimum input arrival time before clock: 2.403ns
Maximum output required time after clock: 20.073ns
Maximum combinational path delay: No path found