madhusudhan_prabhu
Newbie level 4
Hi All,
I want to know what are timing checks in testbenches (VHDL, Verilog or System C)? types of timing checks that exists? How to implement it in any one of the above mentioned HDL languages?
Thanks,
Madhu
I want to know what are timing checks in testbenches (VHDL, Verilog or System C)? types of timing checks that exists? How to implement it in any one of the above mentioned HDL languages?
Thanks,
Madhu