Timing and logic stage for FPGA

[davyzhu]

Below cited from Xilinx techxclusive, but how about the fan out of each net have relationship to the wide function inputs? And some one told me the perfect logic stage is not larger than 3, how many stages will you choose? And a stupid question: where to set this parameter in ISE?

If you want to run at 200MHz in a Virtex-II -5 part (delay through LUT to X/Y output is 0.44 ns), you should limit the code to use no more than 6 logic levels before being registered. That amounts to a 4096-bit wide function implemented in 6 levels of logic, and it could still meet timing. This is not a likely function and may be somewhat limiting since you have to keep in mind the fan out (albeit a limited factor in Virtex-II) of each net. You must also consider the placement of that logic. In other words, give yourself a cushion to allow for placement and routing — you might therefore limit the function to 256 inputs, which is still a very wide function.

DAVY

 

[mark_yeh]

what dose "logic levels" mean? and how to decrease the logic levels in HDL code? thanks.

 

[taotaocui]

The best way is in your HDL code.
If you target to run above 200MHZ, you must register the combinational results as more as possible.
That's to say, between the two levels registers, you combination circuits can't much larger.

 

[davyzhu]

"logic levels" is the levels of LUT in your combinational logic.