time scale selection in verilog

[rama_bing]

How to select timescale (time unit/time precision) for a given design?
Thank you.

 

[ljxpjpjljx]

it releated to your simulation precision!

 

[rama_bing]

Thank you for your reply.
I feel we need precision only for the post layout simulations with SDF annotation(Please correct me if i am wrong).
Are there any other situations in which precision is important ?
What factors we must consider while selecting the timescale for simulation?
Thank you..

 

[cnz]

Just FYI

for rtl, 1ns/10ps
for glv, 1ns/1ps

 

[Syswip]

Are there any other situations in which precision is important ?

During UART, I2C ... etc design.

Syswip,
http://syswip.com/

 

[skyfaye]

Choosing the proper time scale is very important. It will not only impact the correctness of your simulation, but also the time it takes for your simulation. Let's take an example. If your entire design consist of a single file and it only have the following logic:

always @(posedge clk) begin
if (!rst_l)
cpu_interrupt <= #1 1'b0;
else
cpu_interrupt <= #1 s2m_interrupt;
end

Then your timescale can be 1ns/1ns.

But if the code is like this:

always @(posedge clk) begin
if (!rst_l)
cpu_interrupt <= #1.5 1'b0;
else
cpu_interrupt <= #1.5 s2m_interrupt;

Then your timescale need to be 1ns/100ps.

For both examples, you can have even finer timescale (e.g. 1ns/1ps) and your simulation will still work but it will unnecessarily slow down your simulation.

- Hung