eengr
Member level 4
Hi
I am working my way through FPGA prototypes with VHDL examples’ book by Pong P chu. I am trying to simulate the design in Listing 4.15 (dis_mux_test)
Which is as below:
It calls for another VHDL file ‘disp_mux’ which is as below:
I changed the constant N to 5 instead of 18 so that I get ‘sel’ updated after 8 cycles (easier to see in simulation). I managed to simulate the file disp_mux and it works fine. Counter counting fine and I get sseg output updated regularly depending upon the ‘sel’ value
However, when I try to simulate ‘disp_mux_test’ file,
It seems like ‘an’ output always staying @ “0111” & that should happen only when “sel” = “11”. So it looks like counter is not working OR I am doing something silly in my test bench.
My test bench is:
Please help
I am working my way through FPGA prototypes with VHDL examples’ book by Pong P chu. I am trying to simulate the design in Listing 4.15 (dis_mux_test)
Which is as below:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity disp_mux_test is Port ( clk : in STD_LOGIC; btn : in STD_LOGIC_VECTOR (3 downto 0); sw : in STD_LOGIC_VECTOR (7 downto 0); an : out STD_LOGIC_VECTOR (3 downto 0); sseg : out STD_LOGIC_VECTOR (7 downto 0)); end disp_mux_test; architecture Behavioral of disp_mux_test is signal d3_reg, d2_reg : std_logic_vector (7 downto 0); signal d1_reg, d0_reg : std_logic_vector (7 downto 0); begin disp_unit: entity work.disp_mux port map ( clk => clk, reset => '0', in3 => d3_reg, in2 => d2_reg, in1 => d1_reg, in0 => d0_reg, an => an, sseg => sseg); -- registers for 4 LED patterns process (clk) begin if (clk'event and clk = '1') then if (btn(3) = '1') then d3_reg <= sw; end if; if (btn(2) = '1') then d2_reg <= sw; end if; if (btn(1) = '1') then d1_reg <= sw; end if; if (btn(0) = '1') then d0_reg <= sw; end if; end if; end process; end Behavioral;
It calls for another VHDL file ‘disp_mux’ which is as below:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity disp_mux is Port ( clk, reset : in STD_LOGIC; in3, in2, in1, in0 : in STD_LOGIC_VECTOR (7 downto 0); -- data input to be displayed on corresponding 7 seg an : out STD_LOGIC_VECTOR (3 downto 0); sseg : out STD_LOGIC_VECTOR (7 downto 0)); end disp_mux; architecture Behavioral of disp_mux is -- refreshing rate around 800Hz (50MHz / 2^16) human eye wont see the difference -- Say if N = 5, we use last two bis as 'sel' -- With each riging edge of clk @ 50MHz we get the following -- 00 000 -- 00 001 -- 00 010 -- ..... -- ..... -- 00 111 -- 01 000 -- 01 001 -- ...... -- ...... -- 10 000 -- ...... -- ...... -- ...... -- This means that for 3 bits we get 8 (2^3) cycles before 5th & 4th bits change to "01" its state -- Then it goes for another 8 cycles before 5th & 4th bits change to "10" -- & then another 8cycles before 5th & 4th bits are "11" -- So the refersh rate is 8 x 20ns = 160ns = 6.25MHz -- So if we use 16 bits + 2 last bits for 'sel' 2^ 16 = 65536 cycles -- 66536 x 20ns = 1.3ms = 763 Hz = 800Hz apprx constant N: integer := 5; -- Change 5 to 18 as we need last two bits + 16 bits signal q_reg, q_next : unsigned (N-1 downto 0); signal sel : std_logic_vector (1 downto 0); begin -- register process (clk, reset) begin if (reset = '1') then q_reg <= (others => '0'); elsif (clk'event and clk = '1') then q_reg <= q_next; end if; end process; -- next state logic for counter q_next <= q_reg + 1; -- 2 MSBs of counter to control 4 - to -1 multiplexing sel <= std_logic_vector (q_reg (N-1 downto N-2)); process (sel, in0, in1, in2, in3) begin case sel is when "00" => an <= "1110"; sseg <= in0; when "01" => an <= "1101"; sseg <= in1; when "10" => an <= "1011"; sseg <= in2; when others => an <= "0111"; sseg <= in3; end case; end process; end Behavioral;
I changed the constant N to 5 instead of 18 so that I get ‘sel’ updated after 8 cycles (easier to see in simulation). I managed to simulate the file disp_mux and it works fine. Counter counting fine and I get sseg output updated regularly depending upon the ‘sel’ value
However, when I try to simulate ‘disp_mux_test’ file,
It seems like ‘an’ output always staying @ “0111” & that should happen only when “sel” = “11”. So it looks like counter is not working OR I am doing something silly in my test bench.
My test bench is:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY tb1 IS END tb1; ARCHITECTURE behavior OF tb1 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT disp_mux_test PORT( clk : IN std_logic; btn : IN std_logic_vector(3 downto 0); sw : IN std_logic_vector(7 downto 0); an : OUT std_logic_vector(3 downto 0); sseg : OUT std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal btn : std_logic_vector(3 downto 0) := (others => '0'); signal sw : std_logic_vector(7 downto 0) := (others => '0'); --Outputs signal an : std_logic_vector(3 downto 0); signal sseg : std_logic_vector(7 downto 0); -- Clock period definitions constant T : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: disp_mux_test PORT MAP ( clk => clk, btn => btn, sw => sw, an => an, sseg => sseg ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for T/2; clk <= '1'; wait for T/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. sw <= "01010101"; btn(3) <= '1'; for i in 1 to 25 loop wait until falling_edge (clk); end loop; btn(3) <= '0'; --************************ -- test btn(2) operation --************************ btn(2) <= '1'; for i in 1 to 25 loop wait until falling_edge (clk); end loop; btn(2) <= '0'; --************************ -- test btn(1) operation --************************ sw <= "11110101"; btn(1) <= '1'; for i in 1 to 25 loop wait until falling_edge (clk); end loop; btn(1) <= '0'; --************************ -- test btn(0) operation --************************ sw <= "11110101"; btn(0) <= '1'; for i in 1 to 25 loop wait until falling_edge (clk); end loop; btn(0) <= '0'; --****************************** --terminate Simulation --****************************** assert false report "NS Simulation Completed" severity failure; end process; END;
Please help