threshold voltage vs. channel length

[fuxinmingming]

Hi guys,

I simulated NMOS's threshold voltage(VGS=VDS=1V, VSB=0):

10u/6u:770.51mV;
10u/5u:772.03mV;
10u/4u:774.31mV;
10u/3u:778.14mV;
10u/2u:785.87mV;
10u/1u:805.82mV;
10u/0.6u:799.41mV;
10u/0.5u:775.43mV;

Why do the threshold voltage becomes bigger first and smaller later ??

Regards

 

[rob1012]

this may have something to do with a phenomenon called channel length modulation... when a certain limit is reached wherein you make the channel length thinner and thinner the voltage threshold needed to overcome also becomes smaller.

 

[palmeiras]

HI fuxinmingming,

In my opinion there is no straight forward answer for this question. It is the second order effects. In first approximation, the threshold voltage does not depend on channel length (or “the channel length modulation”.
Have you tried to decrease even more the value of length? I would not be surprise if you check a higher value than 755.43 mV.
Regards.

 

[dick_freebird]

If VGS is pinned how are you simulating VT? Just reading
off some .OP result?

It could just be some modeling trickery to get the right
geometry fit against real devices (which have delta L,
DIBL, channel length modulation going on).

 

[nus_lin]

Dear fuxinmingming,

cong to you for finding this. we call it "reverse-short-channel" effect. some good designer's intentionally adjust the length of device to get a minimum Vth for low-voltage design.