The results of using multiple always blocks for signals?

[sree205]

RTL question

Hi,
Assuming the same clock source is used for the entire design, what are the pros and cons of using multiple always blocks for different signals, i.e. one always block for one signal and so on ? I thought this helps in debugging.

Is it advisable to use only a single always block for the entire design ? If so, the different signals, if they have different conditions, will be bunched together in one always block. Is there any advantage of doing it this way ?

 

[deva_eda]

RTL question

Sree,

I am not sure if there is a concrete answer for your question.

But recently in one conference I have come to know one of the advantages of using different always block for different signals is that it helps the verification engineer to get his target code coverage with fewer testcases.

You might have already got the answer .. how ?

Any ways it is always good to have different set of signals ( i mean independent to each ) in a different always block.

More further I would see the methodology to use always blocks is according to the purpose to be acheived from that particular block. For example the next state decoding logic of a FSM. A particular situation or case in design can be acheived in many different ways, but there are factors that decided which one to choose. Some of them .. readability ( definetly problem when you use only one always block ), further EDA tools performance let is be either simulator or synthesis or STA.

Further I strongly disagree that entire design should be coded in one always block. For example how would you/we tackle in case my design requires more than one FSM ?

Cheers

 

[sree205]

RTL question

Is there any document or manual supporting this arguement ? I personally feel that if there r different always blocks, it helps in understanding the overall system perspective a little better than if its clubbed into lesser no. of always blocks. but, its just a supposition.

 

[funzero]

Re: RTL question

It is good to use multiple always block to describe your code .
if you use only single always block in your code , it will function right .
but it will result an very slow simulation performance .
for there are so many signals in the sensitivity list .

 

[sree205]

RTL question

we are talking about synchronous design here. so, no question of multiple signals in the sensitivity list. if u see my first post, i would have mentioned a single clock source being used.

 

[avimit]

Re: RTL question

Using a single always block is a bad design practice. Its difficult to maintain and debug.
Multiple always blcok is more structured approach.
In a single always style of coding, you will read the signals, which are assigned in the same always block, which can eaisly introduce unintentional errors. Again you will have to be very very careful about non-blocking and blocking assignments.

Again there is nothing functionally wrong in using one always blcok style of coding, its just seems like a big mess.
Hope it helps,
Aviral Mittal

 

[Nithin_eda]

Re: RTL question

Using multiple always blocks slows down simulation, because for each always block the event queue is triggered which causes simulation to slow.If u use a single always block the event queue is triggered only once which helps in the simulation to speed up. O.K as far as understanding the code multiple always blocks might help but ur simulation speed will go down. There is a paper on various coding styles which help in speeding up simulation.
http://www.sunburst-design.com/papers/CummingsICU1997_VerilogCodingEfficiency.pdf

Thanks,
Nithin

 

[yaseen1]

Re: RTL question

Blodocking assignment

Added after 1 hours 22 minutes:

It is good

 

[benzwishc]

Re: RTL question

using multiple always or process not only make it easy for simulation,but also make it more efficient for synthsis.customly we are inclined to have follows rules when we write rtl codes:1 funtion-related combinational logic in one always or process 2 do not have multiple clocks in one always or process unless the sync circuits 3 have FSM in independent always or process, of course there are others rules, you can refer to some paper about synthsis

 

[sree205]

RTL question

Hi Nitin_eda,
i read the paper. In the introduction itself, it says that its useful for models and testbenches. will the same guidelines be applicable for RTL ?

 

[Nithin_eda]

Re: RTL question

For RTL it doesn't matter if u use a single always block or multiple always blocks, because the synthesized circuit in both the cases will be the same.

Thanks,
Nithin

 

[bronzefury]

Re: RTL question

It does matter if you have a single always block with a huge sensitivity list vs multiple always blocks with only a few signals that are important for that particular piece of logic.

Having a single always block with many input signals usually compiles to something larger and more complicated than many small always blocks. This can easily be verified by taking a look at a synthesized result. One huge, single always block is more difficult to maintain, may trigger due to unintended signals, and is difficult to debug.

Simulation may or may not speed up. This is not the issue. What is important is that hardware is modeled and is functioning properly. Speed can easily be increased by purchasing memory or faster computers - both relatively chip nowadays. Real hardware is composed of many small blocks of logic.

Make your life easier by coding with smaller blocks.

 

[Nithin_eda]

Re: RTL question

u can see in the question the first statement itself its written that it is a synchronous always block. so how does ur always block get triggered with variation in signals other than clock. when u r using a single always block or multiple always block with the same triggering condition, the synthesized ciruit will be the same and that's for sure.Maintainability and debugging is ur problem

 

[bronzefury]

Re: RTL question

Nithin, it does not imply that there is one synchronous always block. He just mentions that it is a design sourced by one clock. So, the design most likely contains a mixture of flops in a single clock domain and combinational logic.

 

[Nithin_eda]

Re: RTL question

Ok say if there is combo and one clock or say two clocks, then I can use all the signals changing on a particular clock in one always block and all the combo logic in another always block. I think there should be no problem in that.
always @ (posedge clk1)
begin
........
end
always @ (posedge clk2)
begin
........
end
// for combo
always @ *
begin
........
end

Thanks,
Nithin

 

[bronzefury]

Re: RTL question

If that combo block contains one state machine then I don't see a problem either. But if you are mixing state machines within one combo block, then you've got a problem (or rather, a major headache).

 

[love2read]

RTL question

one always for one signal would better

 

[incisive]

Re: RTL question

If u r using a synch single clock y dou need input signas in the sensitivity list?A clock and reset should be applicable. and if there is a combo logic inside a always block then only simulation matters. finally, all we want is a successful synthesizable RTL code with out any setup and hold timeviolations and perfect timing which doesnt matter if multiple always or single clock.

regards
incisive