Testbench compiling error: Identifier 'unsigned' not visible

[guiliu]

modelsim identifier is not directly visible.

I used type 'unsigned' for my entity, and every thing was fine for compilation, but when I tried to compile the testbench (the component is exactly same as the entity), it sais

Identifier 'unsigned' is not visible. Making two objects with the name 'unsigned' directly visible via use clauses results in a conflict; neither object is made directly visible. (LRM Section 10.4)


If I modify the port type in the component declaration, then there will be elaboration problem since the component does not match the entity.

How to sovle this problem? Thanks a lot!

 

[aji_vlsi]

identifier is not directly visible.

I used type 'unsigned' for my entity, and every thing was fine for compilation, but when I tried to compile the testbench (the component is exactly same as the entity), it sais

Identifier 'unsigned' is not visible. Making two objects with the name 'unsigned' directly visible via use clauses results in a conflict; neither object is made directly visible. (LRM Section 10.4)


If I modify the port type in the component declaration, then there will be elaboration problem since the component does not match the entity.

How to sovle this problem? Thanks a lot!

Assume you use VHDL. Show us the library/use clause in your testbench. i.e. something like:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Looks from the error like you have made 2 packages visible and both contain declaration of type unsigned. Which tool do you use?

HTH
Ajeetha, CVC
www.noveldv.com

 

[guiliu]

identifier unsigned is not directly visible

Yes, it is VHDL, I use Modelsim as simulation tool, here are the library clauses.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


Thanks in advance!

 

[aji_vlsi]

identifier unsigned is not directly visible.

Yes, it is VHDL, I use Modelsim as simulation tool, here are the library clauses.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


Thanks in advance!

Why do you use all these libraries? Strictly speaking you only need ieee.numeric_std.all Try the following:

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

You may hit few other issues with this - let me know what you get, I will see if I can help

Ajeetha, CVC
www.noveldv.com

 

[guiliu]

vhdl identifier unsigned is not directly visible.

Thank u so much, vji_vlsi.

I have tried to compile with different libraries. I found that the library ieee.std_logic_unsigned.all does nothing to do with the Identifier 'unsigned' is not visible problem.

The problem happens on ieee.std_logic_arith.all , if I don't use this library, there will be problems for typecasting, for instance : a <= UNSINGED(b); as <= CONV_STD_LOGIC_VECTOR(i, 6) etc. If I use this library, there will be no typecasting problem, but the Identifier 'unsigned' is not visible problem occures.

Could u help pls? Thanks a lot!

 

[aji_vlsi]

indetifier unsigned is not directly visible

Thank u so much, vji_vlsi.

I have tried to compile with different libraries.

Just use the IEEE standard libraries - i.e.
ieee.std_logic_1164.all;
ieee.numeric_std.all;

I found that the library ieee.std_logic_unsigned.all does nothing to do with the Identifier 'unsigned' is not visible problem.
The problem happens on ieee.std_logic_arith.all ,

Do NOT use these non-standard ones.

if I don't use this library, there will be problems for typecasting, for instance : a <= UNSINGED(b); as <= CONV_STD_LOGIC_VECTOR(i, 6) etc.

This CONV_STD_LOGIC_VEC* stuff is NON-STANDARD (though it has been used in the past). Use to_integer instead.

Read FAQ at www.vhdl.org/comp.lang.vhdl/

HTH
Ajeetha, CVC
www.noveldv.com