Test Bench Problem for HEAP

[Pourrahim]

Hi
I was trying to write a Test bench for HEAP and simulate it using nclaunch (Cadence). But I cant get acceptable results. For some reason I do not have my input (din) in my wave form. Here is the wave form and the code and the test bench. can any one help me with this

**broken link removed**

Here is the Code

// Model of a heap.
//
// The heap holds WORDS keys, each of BITS bits ordered in ascending order.
// Keys may repeat.  The key in first position is always a minimum key.
//
// The heap supports 4 operations:
//
// - NOOP: remain idle
// - PUSH: add a key to the heap if it is not full
// - POP : remove the first element from the heap if it is not empty
// - TEST: check the heap property
//
// When ready is asserted, dout gives the minimum value of the keys held
// in the heap.  Commands are accepted only when ready is asserted.
//
// The number of bits in a key is the logarithm of the number
// of slots in the heap, so that all keys may be distinct.

// Author: Fabio Somenzi <Fabio@Colorado.EDU>

//typedef enum {NOOP, PUSH, POP, TEST} Op;
//typedef enum {IDLE, PUSH1, PUSH2, POP1, POP2, POP3, TEST1, TEST2} State;

module heap(clock,cmd,din,dout,ready,full,empty,error);
    parameter      BITS = 2;
    parameter 	   WORDS = 4;
    parameter 	   MSW = WORDS-1;
    parameter 	   MSB = BITS-1;
    
	// FOR State
	localparam IDLE = 3'b000;
	localparam PUSH1 = 3'b001;
	localparam PUSH2 = 3'b010;
	localparam POP1 = 3'b011;
	localparam POP2 = 3'b100;
	localparam POP3 = 3'b101;
	localparam TEST1 = 3'b110;
	localparam TEST2 = 3'b111;
	
	// FOR CASE
	localparam NOOP = 2'b00;
	localparam PUSH = 2'b01;
	localparam POP = 2'b10;
	localparam TEST = 2'b11;
	
	input 	   clock;
    input 	   cmd;
    input [MSB:0]  din;
    output [MSB:0] dout;
    output 	   ready;
    output 	   full;
    output 	   empty;
    output 	   error;

   // Op wire        cmd;

	reg [2:0] State;
    reg [BITS:0]   nitems, posn;
    reg [MSB:0]    h0, h1, h2;
    reg [MSB:0]    h [0:MSW];
  //State reg      State;
    reg 	   error;
    wire [BITS:0]  prnt, lft, rght;
    integer 	   j;

    initial begin
	State = IDLE;
	nitems = 0;
	posn = 0;
	h0 = 0;
	h1 = 0;
	h2 = 0;
	error = 0;
	for (j = 0; j < WORDS; j = j+1)
	  h[j] = 0;
    end

    assign dout = h[0];
    assign ready = State == IDLE;
    assign full = nitems == WORDS;
    assign empty = nitems == 0;

    function [BITS:0] parent;
	input [BITS:0] i;
	reg [BITS:0] tmp;
	begin: _parent
	    tmp = i-1;
	    parent = {1'b0,tmp[BITS:1]};
	end
    endfunction // parent

    function [BITS:0] left;
	input [BITS:0] i;
	begin: _left
	    left = {i[BITS-1:0],1'b0} + 1;
	end
    endfunction // left

    function [BITS:0] right;
	input [BITS:0] i;
	reg [BITS:0] tmp;
	begin: _right
	    tmp = i+1;
	    right = {tmp[BITS-1:0],1'b0};
	end
    endfunction // right

    always @ (posedge clock) begin
	case (State)
	  IDLE:
	    case (cmd)
	      PUSH: if (full == 0) begin
		  posn = nitems;
		  h0 = din;
		  nitems = nitems + 1;
		  State = PUSH1;
	      end
	      POP: if (empty == 0) begin
		  nitems = nitems - 1;
		  posn = 0;
		  h0 = h[nitems]; // watch out for the extra bit!
		  h[0] = h0;
		  State = POP1;
	      end
	      TEST: begin
		  posn = 1;
		  error = 0;
		  State = TEST1;
	      end

	      NOOP: ;

	    endcase // case(cmd)

	  PUSH1: begin
	      h1 = h[prnt];
	      State = PUSH2;
	  end

          PUSH2: if (posn == 0 || h1 <= h0) begin
	      h[posn] = h0;
	      State = IDLE;
	  end else begin
	      h[posn] = h1;
	      posn = prnt;
	      State = PUSH1;
	  end

	  POP1: begin
	      h1 = h[lft];
	      State = POP2;
	  end

	  POP2: begin
	      h2 = h[rght];
	      State = POP3;
	  end

	  POP3: begin
	      if (lft < nitems && h1 < h0 &&
		  (rght >= nitems || h1 <= h2)) begin
		  h[posn] = h1;
		  posn = lft;
		  State = POP1;
	      end else if (rght < nitems && h2 < h0) begin
		  h[posn] = h2;
		  posn = rght;
		  State = POP1;
	      end else begin
		  h[posn] = h0;
		  State = IDLE;
	      end
	  end

	  TEST1: if (posn >= nitems) begin
	      State = IDLE;
	  end else begin
	      h1 = h[prnt];
	      State = TEST2;
	  end

	  TEST2: if (h[posn] < h1) begin
	      error = 1;
	      State = IDLE;
	  end else begin
	      posn = posn + 1;
	      State = TEST1;
	  end

	endcase // case(State)
    end

    assign prnt = parent(posn);
    assign lft = left(posn);
    assign rght = right(posn);

endmodule // heap

and here is my Test bench

// Test bench
module test;
parameter BITS=2;
parameter WORDS = 4;
parameter MSW = WORDS-1;
parameter MSB = BITS-1;

//inputs and outputs
reg clock;
reg [BITS-1:0]cmd;
reg [MSB:0]  din;
wire [MSB:0] dout;
wire ready;
wire full;
wire empty;
wire error;

//Instantiation
heap H (.clock(clock),
		.cmd(cmd),
		.din(din),
		.dout(dout),
		.ready(ready),
		.full(full),
		.empty(empty),
		.error(error));
		

initial begin
clock=1'b0;
cmd=2'b00;
din=2'b00;
end

always begin
cmd= 2'b00;
din= 2'b00;
#9;
cmd=2'b01;
din=2'b11;
#9;
cmd=2'b11;
din=2'b10;
#9;
din=2'b01;
#9;

$stop;
end

  
always begin :Clock_Generator
    #5 clock =!clock;
	   end
endmodule

 

[Pourrahim]

I found the answer myself