tcl scripts for RTL compiler

[Yesh]

Hello all,

I am working on a project which mainly concentrates on processing of EEG signals. Half of the work is done by other teammates (i.e., till generation of verilog file). Now i need to convert this verilog file into schematic and layout in digital environment. Can anyone explain me the steps involved in it and necessary materials/website information. I have an idea that, i need to write a script(.tcl script) for generation of net-list from verilog file had.

Please its urgent.

Yeshwanth

 

[slsindorf]

From RTL verilog to layout is a long process that cannot easily be explained in a few sentences.

RTL Compiler can generate a template script for you to start with: if you just execute 'rc', read the text, and you will find something about template scripts.

With the template of choice, timing constraints, and technology libraries, you can make your netlist.