Tail pipeline registers - how they fix the timing issue

[cysco]

Tail pipeline registers

How do these registers fix the timing issue when using adaptive scan?
Thanks.

 

[santhosh007]

Re: Tail pipeline registers

you will have extra clock cycles( equal to no of pipeline stages) are available to close the time for the scanout to pads instead of meeting the scanout to pad in single clock cycle.

 

[cysco]

Re: Tail pipeline registers

But I see someone said:
When DFTmax scan compression is used,
compression block can produce excessive toggling on scan output pads.
To prevent this, clocked output shall be used (tail registers).

Do you agree.