sythesis & simulation , FPGA & CPLDs ,frontend & backend

[renoz]

hi all

i want to know about difference between sythesis & simulation , FPGA & CPLDs ,frontend & backend and what kind of softwares used above

waiting for ur reply

 

[rca]

oh, that some basic stuff:
1- write spec/verification plan
2- write RTL & TB
3- write tests (simulation)
4- this code could test ON FPGA or CPLD (two differents technologies, depend of your goal)
5- synthesis/DFT to your technology target
6- place/CTS/hold/Route
7- STA
8- along 5-6-7, LEC & ATPG

1 to 3 is mainly the frontend
5 to 8 is mainly the backend

depending of the fpga goals, from only checks in reel world and for firmware/software development or for sell contain in fpga (I don't know the trade off of this)

 

[sns22]

When you synthesize a code you are actually going to put it in hardware and it generates fitter settings,but simulation is only for conformation of code with respect to time instance.for example some statements such as (wait for 1 ns, after 20 ns) is not
synthesizable because in HW one cannot ask to wait for a particular time.But in simulation you check that your results arrive
after a wait of 1 ns..We do this to make sure that if a signal a changes based on signal b, signal b is stable enough to make
change in signal a.if signal b is changing at the same time as signal a output may not be stable. simulation just give you an idea of how the HW will function at a particular time stamp.

 

[renoz]

Thank uuuu for ur deep explanation

---------- Post added at 12:15 ---------- Previous post was at 12:11 ----------

Thank uuu,but i dont know about STA,LEC & ATPG