korgull
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system verilog parameter
Hi,
Well, now that I seemed to have solved my problem finding a conversion of the VHDL 'LENGTH command, I now have a problem with the way I want to use it.
I would like to use the $size command to define variables in a bit width. For example I thought that I could do this..
so that I could do this:
Unfortunately, I cannot place the $size command in there as it tells me that I have an "Illegal operand for constant expression" Furthermore, I need to place the "parameter" code in the beginning, which isn't the most ideal place for it for what I want to do as I need my function to be recursive.
Is there a way that I can establish an equation that defines the bit width of "X" and "Y"? Or does it have to be defined with the parameter statement.
thanks
Hi,
Well, now that I seemed to have solved my problem finding a conversion of the VHDL 'LENGTH command, I now have a problem with the way I want to use it.
I would like to use the $size command to define variables in a bit width. For example I thought that I could do this..
Code:
parameter XH = ($size(X) - 1);
parameter XMU = ($size(X) / 2);
parameter XML = (($size(X) / 2) - 1);
Code:
a1 = X[XH:XMU];
a0 = X[XML:0];
b1 = Y[XH:XMU];
b0 = Y[XML:0];
Is there a way that I can establish an equation that defines the bit width of "X" and "Y"? Or does it have to be defined with the parameter statement.
thanks