SYstem Verilog Interface

[vpillai]

Hi,

I am planning to use System Verilog Interface for connecting ports through the design hierarchy.
Does people use interface in the design RTL side ?
Does all the tools (like Spyglass, LEC, Synopsys DC etc) understands it?

Don't want any of the EDA tool to barf on it later.

Regards,
Velu

 

[narfnarf]

Hi vpillai,

I can only speak for Synopsys DC. My experience with DC is that it supports some but not all SV interface features. Off the top of my head, I remember using it to replace a group of wires successfully, but I don't think it supports interface modports and chokes on that. But this was a couple months (w/ 2009.06) back so YMMV. At our company, the policy is V2k1 for synthesizable RTL and SV for Verification.

narfnarf

 

[vpillai]

Hi narf,

Thanks for the reply.

Is there any commercial tool or script available for stitching up RTL modules hierarchically?

Regards,

Velu

 

[narfnarf]

Yes, we use emacs verilog-mode. Verilog-mode - Intro - Veripool

narfnarf