Synthsis error using DC

[bzaki]

Hi

i'm a design compiler beginner and i faced an error in the analyze step. This error is produced when i use a function in port mapping(instaintiating a component). For example

myunit: TESTCOMPONENT Generic Map(input_size) port map(INPUT_A(My_Function(input_size) downto 0),Output);

The error=>"Signal or port name expected as actual in association element"

this error can be overcomed by assigning the function to a temporaray signal outside the port map as:
INPUT_A_temp <=INPUT_A(My_Function(input_size) downto 0);
myunit: TESTCOMPONENT Generic Map(input_size) port map(INPUT_A_temp,Output);

Moreover, when i instantiate a component in a 'FOR .. GENERATE' statement, so i have to use a 2D array as a temporary signal.However, if the signal
inside the port map is a 2D array, then, i have to use a 3D array which is not synsiziable!!

I appreciate any help or hints.

Thanks in advance