ashrafsazid
Advanced Member level 4
Hi Altruists,
Can anybody please suggest me how can I make a quarter cycle "synthesized" delay as like as the figure below?
The clock pulses here have a period of 200ns. The behavioral Verilog code was written by assigning a #delay to the signal. As like as below:
`timescale 1ns/1ps
@(posedge main_clk) begin
clk_violet = high
clk_orange = #50 high
But I cannot solve it out to make a delay with synthesizable code. Please help.
Can anybody please suggest me how can I make a quarter cycle "synthesized" delay as like as the figure below?
The clock pulses here have a period of 200ns. The behavioral Verilog code was written by assigning a #delay to the signal. As like as below:
`timescale 1ns/1ps
@(posedge main_clk) begin
clk_violet = high
clk_orange = #50 high
But I cannot solve it out to make a delay with synthesizable code. Please help.