biju4u90
Full Member level 3
Here are my process statements for a 4:1 mux using 'if-elsif' and 'case' statements in VHDL.
When I synthesized them in Spartan 3E, I got the same synthesized reports!! The technology schematic also looked the same!! How this is possible??
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 process (A,B,C,D,sel) begin if (sel = "00") then Y <= A; elsif (sel = "01") then Y <= B; elsif (sel = "10") then Y <= C; else Y <= D; end if; end process;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 process (A,B,C,D,sel) begin case (sel) is when "00" => Y <= A; when "01" => Y <= B; when "10" => Y <= C; when others => Y <= D; end case; end process;
When I synthesized them in Spartan 3E, I got the same synthesized reports!! The technology schematic also looked the same!! How this is possible??
Code:
=========================================================================
Final Results
RTL Top Level Output File Name : mux_case.ngr
Top Level Output File Name : mux_case
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 7
Cell Usage :
# BELS : 3
# LUT3 : 2
# MUXF5 : 1
# IO Buffers : 7
# IBUF : 6
# OBUF : 1
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s100evq100-5
Number of Slices: 1 out of 960 0%
Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 66 10%
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