synthesizeable verilog code

[siva_7517]

hi ,
I am tyring to write a code for floating point in verilog, but facing a problem when synthesis. The multiplication is:

data_out = 0.707 x data_in

My coding is written below:

module multiply (data_in, clk, data_out);
input [7:0] data_in;
input clk;
output [7:0] data_out;
reg [7:0] data_out;
reg [9:0] state1;
reg [14:0] temp;

parameter state1 = 10'b 1010011011;

always (@posedge clk)
begin
temp <= data_in * state1;
data_out <= temp << 10;
end
endmodule

Plz correct me if there is error in my coding.
Thanx

 

[thedesolatesoul]

Code looks perfect to me.
What error are you getting and what synthesizer are you using?

 

[siva_7517]

hi,

I am using PKS from cadence to do the synthesis process. After build generic from the RTL coding there is no connection from data_in (open circuit).

siva

 

[tkbits]

Shifting 10 bits and then fitting the result into 8 bits will always produce 0. The assignment to data_out may be optimized to always produce 0.

 

[BOIS]

yes, data_out is always zero and has nothing to do with data_in,the always block is a false path.synthesis tool maybe optimize data_in to no connection,and data_out to ground

 

[ssslin]

i think there were some problems..
a) state1 = 10'b1010011011 , the decimal value is not 0.707 but 0.6514.
b) "always(@posedge clk)" may be always@(posedge clk).
c) the left shifting may be right shifting ,because the state1 value is assumed as multiply 1024 ,so if u want get original 0.707, data_out should be got by right shifting temp.Besides, the width of temp would be [17:0] ,just equal data_in'width add state1'width.