synthesis with level shifters

[stsiligg]

I' m currently trying to make synthesis (with synopsys) a block with 3sublocks which work in diferent voltage. Of cource between these blocks have to be added level shifters. Is there anybody to know how to define the level shifters in the script?

Thank you in advance......

 

[RBB]

I've usually found it easiest to instantiate the level shifters into the RTL.

 

[sam536]

Yes. Below explanation wrto Synthesis with DC.

DC will recognize the design is multivoltage design and utilizes multivoltage capabilities if any of below three conditions are met.
1) instance based OC specified.
2) The -mv_mode with dc_shell-t
3) Subsets of Target lib

Level shifter cells are required to connect drive and load pins operating at different voltages across the power domains. These cells are modelled either as simple or buffer cells with enable pins. Usually, we prefer to use enable type level shifters when power domains of desin must be powered on and off independently .

Buffer type level shifters can be inserted by running complie(compil_ultra) or insert_level_shifters command.
Command : insert_level_shifters -preserve nets -all_clock_nets library_cell_name -clock_net clock_name -verbose

check the man pages if required.

Enable type level shifters can be inserted by running complie(compil_ultra) or insert_isolation_cell command.
Command : insert_isolation_cell -object_list nets -reference library_cell_name -enable port|pin|net -force

After　inserting the Level shifters, check the design how level shifters are inserted using below command.
check_level_shifters -verbose

Hope you got it...

Regards,
Sam