e-bedlam
Newbie level 4
Can some one help me to define SDC constraints on the output of the MUX (at the extreme end.)
If i give :
clock_generated_clock -source CLK -divide_by 1 [get_ports o_mux]
then the sequential path is left out but if i give :
clock_generated_clock -source CLK -divide_by 2 [get_ports o_mux]
then the combo path is left out from being constrained by the tool.
So how do i constrain both the paths.
Are we allowed to to put two clocks on the output of the mux. I mean can we mention both of the above constraints.
Thanks in advance.
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